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How to get deep hierarchy signals in top entity in NC-VHDL?
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roger



Joined: 27 Aug 2003
Posts: 182
Helped: 7
Post18 Sep 2003 7:23   

init_signal_spy modelsim
in verilog we can use
wire signal=top.module1.module2.signal;

in modelsim we can use
init_signal_spy("../.../signal", signal1);

But in NC-VHDL
how can we got internal signal rather than using port mapping?

Help me please
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roger



Joined: 27 Aug 2003
Posts: 182
Helped: 7
Post19 Sep 2003 6:33   

init_signal_spy cadance
see pdf ncvhdl.pdf

C:\Program Files\Cadence Design Systems\LDV\doc\ncvhdl

ncvhdl.pdf utilities nc_mirror
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sajeev_antony



Joined: 12 Sep 2002
Posts: 21
Location: India
Post19 Sep 2003 12:08   

init_signal_spy
I downloaded the signal_spy packeg from model.com.
could u pls explain me where to put those files and how to use it.


roger wrote:
in verilog we can use
wire signal=top.module1.module2.signal;

in modelsim we can use
init_signal_spy("../.../signal", signal1);

But in NC-VHDL
how can we got internal signal rather than using port mapping?

Help me please
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Post19 Sep 2003 12:08   

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roger



Joined: 27 Aug 2003
Posts: 182
Helped: 7
Post12 Jun 2004 5:06   

modelsim hierarchy
how to use it

add the lib header

library modelsim.lib;
use modelsim_liob.util.all;

...
...
begin

init_signal_spy("??/??/??","signal_name",0);

you canrefer to the modelsim user manual
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