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mueller5321
Joined: 27 Mar 2002
Posts: 22
Location: Germany
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 11 Sep 2003 15:21 non-multiplexed to multiplexed bus problem |
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For a design i have to couple a SJA1000 Can Controller with multiplexed
(Intel) interface (/RD,/WR,ALE) to a Motorola
MC68332 with have only non-multiplexed Address and datalines.
Have anybody already a solution for this problem?
Or can give me some hints.
THe other direction (multiplexed to non-multiplexed) is easy solved with a latch.
Have anybody already a design for this?
Regards
Max
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sheikhu
Joined: 16 Sep 2003
Posts: 7
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| 16 Sep 2003 4:07 Re: non-multiplexed to multiplexed bus problem |
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| i am not sure .... but can't u non-multiplex the data from Intel one if u manage to read the select bits ???
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jzo777n
Joined: 10 Sep 2002
Posts: 113
Helped: 2
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| 16 Sep 2003 7:18 Re: non-multiplexed to multiplexed bus problem |
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I have once connected an Intel 82526 to a MC68332 with the same problem
My solution was to multiplex the bus with a buffer, a transceiver and a PLD.
There is one other solution if you could accept a little overhead and that is to first write the address with the help of one other chipselect connected via a inverter to AS/ALE and then do the read/write with a second chipselect.
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mueller5321
Joined: 27 Mar 2002
Posts: 22
Location: Germany
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| 16 Sep 2003 9:59 Re: non-multiplexed to multiplexed bus problem |
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Maybe you mean the 82257 instead of 82256?.
This have i also already done. There the only problem is the Ready to DSACK conversion, because the Ready did go to late to ready.
The 82257 have also a mode which can handle the standard 6833x bus (non-multiplexed). So no big problem. (only if the 82257 did not response anymore, like happend to me-> buserror).
At the beginning i think also about a solution with only 2 to 1 multiplexer and buffer and a few gates, but the timing is then not according specificatin.
THe next step was a single CPLD but there the account of the 3 x 8 bits of the Ports let increase the design-size very much.
The latest try is with a 245, a 244 and also a PLD, which use a 4 registers as shiftregister for a 2 phase counter and controlpattern for the buffers control lines. The fastest solution need 2 waitstates. And the Dsack is also generated if you don't want use the internal WS generation 
There seams to be a company which also use a CPLD (JANZ) but they need 5 waitstates for the same problem:-)))
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jzo777n
Joined: 10 Sep 2002
Posts: 113
Helped: 2
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| 18 Sep 2003 7:27 Re: non-multiplexed to multiplexed bus problem |
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Nope, I mean 82526, it’s was the predecessor to 82527.
I have also used the 82527 to a 683xx, but as you say it is easier.
For the 82526 I used a 244, 245 and a PLD as your latest solution.
I am not sure how much I used of the PLD to control the 82526 because it was some time ago and it controled other stuff also.
Could even be so that it was the Hitachi H8/500 I connected it to. Hm…
Sorry, but I am sure that I used a 244, 245 and a PLD to interface the chip
If you considering the other method with a CS to ALE/AS,
you must also be aware that you can’t do read-modify-write cycles as bit-set/reset instructions
and it isn’t a atomic operation so if there are a interrupt which access the chip you must turn off the interrupt.
But it's a cheap and small space solution.
Best regards
jzo777n
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kib
Joined: 27 Mar 2003
Posts: 121
Helped: 7
Location: Bangalore, India
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| 20 Sep 2003 7:54 Re: non-multiplexed to multiplexed bus problem |
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| use an CPLD for implementing the logic
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mueller5321
Joined: 27 Mar 2002
Posts: 22
Location: Germany
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| 20 Sep 2003 10:23 Re: non-multiplexed to multiplexed bus problem |
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| kib wrote: |
| use an CPLD for implementing the logic |
You are really great
Read the upper postings. You will see we already taked about it.
It is simple really indeed but you have to spend 24 pins just for nothing.
If you compare the costs and what you get, you will see, that a 244, a 245 and a small PLD (S or C) will do the job great.
Regards
Max
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