Comparison of VHDL, Verilog, and System verilog

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Comparison of VHDL, Verilog, and System verilog

EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design

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niks

Joined: 18 Mar 2002
Posts: 189
Helped: 2

23 Jul 2003 9:52 Comparison of VHDL, Verilog, and System verilog

Its a very good whitepaper.

http://www.model.com/resources/languagepaper/default.asp

~niks~

michland

Joined: 25 Jul 2002
Posts: 10

23 Jul 2003 12:02

Distinct comprasion. Thanks.

Q: Do you know about using AHDL in non-@ltera projects? In comparison with VHDL/Verilog it's more usefull for syntesable work.

steshenko

Joined: 31 May 2002
Posts: 67
Helped: 1

23 Jul 2003 12:41

AHDL can't use in non @ltera project, because it use specific @ltera primitives and orient on @ltera tools. As you know, no third companies tools support AHDL.

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