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keshexinxin
Joined: 29 May 2003
Posts: 10
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 22 Jul 2003 12:28 help DFT question? |
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Now I use the synopsys DFT to add scan chain after synthesis the verilog code.
before I insert_scan . I do check_test command . and the DC give me some information like that
Information : Inferred system/test clock port XCLK(20,0,30,0).(TEST-260)
Information : Inferred system/test clock port XCLK(20,0,30,0).(TEST-260)
Information : Inferred system/test clock port XCLK(20,0,30,0).(TEST-260)
but before I check test . I define the test protocol and create only one test clock XCLK (20,0,30,0). I don't know how can I get the other two systerm clock . and how to get rid of them.
btw . I use the synopsys 2002.05 ver
thanks for help
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keshexinxin
Joined: 29 May 2003
Posts: 10
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| 22 Jul 2003 12:33 |
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oh sorry . I make a mistake about the information .
the information like this
Information : Inferred system/test clock port XCLK(20,0,30,0).(TEST-260)
Information : Inferred system/test clock port CPU_ADDR[1](22,5,27,5).(TEST-260)
Information : Inferred system/test clock port CONF[1](22,5,27,5).(TEST-260)
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alanray
Joined: 11 Jul 2002
Posts: 22
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28 Jul 2003 3:31 TESTCLK GEN |
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| Did your design have internal gate clock
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johnnyh
Joined: 09 May 2002
Posts: 34
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| 02 Sep 2003 10:31 |
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| please post your script file, just the error message cannot debug.
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