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Tetra
Joined: 19 Jun 2003
Posts: 16
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 22 Jul 2003 10:25 spartan pin LOC problem |
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The problem summrized in the following steps
1- I need to assign certain pins pf spartan 2 device so I used different methode to do so (Constrains editor, ucf file gnerated from leonardo, attribute in VHDL file ) all methode gave successful results and the Constraint Editor see the assignments of pins in the required positiones.
2- The MAP step in design manager gave the following error in almost all the assigned pin
"ERROR:MapLib:30 - Bad format for LOC constraint 129 on IBUF. To bypass this
error set the environment variable 'XIL_MAP_LOCWARN'."
3- I did the setting of the required environment variable and the all design flow had been pass successfuly.
4- I reviewed the output report of "PAD report" and I found that the assigned pin location differ greatly from that seen in the constrains editor.
can any one help.
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karlheinz
Joined: 09 Feb 2003
Posts: 35
Helped: 1
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| 22 Jul 2003 11:47 spartan pin LOC problem |
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Hi Tetra,
I think your problem is, that you try to use a primitive (the IBUF) on
a pin that doesn't has this one.
Could you be more specific, which device, which case, which pin number ?
HG
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Tetra
Joined: 19 Jun 2003
Posts: 16
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| 22 Jul 2003 12:09 |
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Regarding the device is SpartanII XC2S100-5PQ144.
regarding the Case and pin number, I did an experiment that a NAND fate and assigned the 3 terminals with I/O ports and I got the same results.
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zape
Joined: 10 Jul 2003
Posts: 104
Helped: 9
Location: Spain
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| 22 Jul 2003 12:34 |
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1. Are you sure that the LOC syntax is right? I mean i.e.: NET "XX" LOC = "P99"; Check the information from XILINX.
2. About the "XIL_MAP_LOCWARN" I will restore it previous value. It only avoids the warnings.
3. I donīt remember exactly the version, perhaps ISE 4.1, but a bug related to the constraints editor was reported.
4. Send your design for giving you more help.
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zape
Joined: 10 Jul 2003
Posts: 104
Helped: 9
Location: Spain
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| 22 Jul 2003 13:28 |
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I have checked Xilinx site and there is no XC2S100-PQ144. See attached files.
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Tetra
Joined: 19 Jun 2003
Posts: 16
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| 22 Jul 2003 13:51 |
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regarding the device it is spartanII 100K gate and -5PQ144 specify speed grad and packaging so it will not change our setuation as the folw stop at certain step. any way
I'm sure that the LOC syntax is right as the translate step passed.
regarding "XI_MAP_LOCWARN" thats right, it is only avoids the warning.
I use 4.1 with windows 98 and target Virtex and non of this error appeared. now I doubt about win 2000 which currently my OS.
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tlp71@hotmail.com
Joined: 14 May 2002
Posts: 451
Helped: 3
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| 23 Jul 2003 10:15 |
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may be that you try to map a reserved or special pin?
I have the same trouble if woud assign the done pin.
Post i will analyze it.
bye.
G.
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Tetra
Joined: 19 Jun 2003
Posts: 16
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| 24 Jul 2003 8:27 |
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Dear TPL71
I avoided the special pins in my design. and to be sure I made a small NAND gat design and I ssigned the three pins into general I/O pins and I got the same error. Dos anyone passed the design flow
Leonardo -- file.edf --> alliance ---> file.bit on win2000 (pentium4 1.5HZ) successfuly ?
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