HDL-93 HDL-180

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visualart

Joined: 21 Dec 2001
Posts: 588
Helped: 26

21 Jul 2003 2:06 HDL-93 HDL-180

I miss the scriptor synthisis the Cusb IP core by synopsys.
Can you help me?
When I run the DC, it report many warnings as follow:
"Potential simulator-synthesis mismatch if index exceeds size of array. HDL -93"
"Variable 'a' is being read in routine .... , but does not occur in the timing control of the block with begins, there. HDL-180"

How can I deal with the warnings?

Tia

jkfoo

Joined: 17 May 2001
Posts: 37

21 Jul 2003 15:02

For HDL-93 warning, if you are sure that your index is never gonna exceed the size of array declared, then you may ignore this warning. As for HDL-180, variable or signal 'a' is not included in the sensitivity lists, you will need to fix this warning. At the end of the day, any mismatch can be captured by running gate-level simulation or formal verification.

visualart

Joined: 21 Dec 2001
Posts: 588
Helped: 26

22 Jul 2003 1:54

Thx jkfoo.
About the HDL-93 , I may ensure and ignore them.

the HDL-180, they are error, when i write as follow:

always @(a[0] or a[1])
begin
b = a
end
Why the varbile 'a' Can not write by 'a[]'?

abner

Joined: 04 Oct 2002
Posts: 24

22 Jul 2003 3:00

visualart wrote:

Thx jkfoo.
About the HDL-93 , I may ensure and ignore them.

the HDL-180, they are error, when i write as follow:

always @(a[0] or a[1])
begin
b = a
end
Why the varbile 'a' Can not write by 'a[]'?

Check bus "a" 's width. If bus "a" is from bit 7 to bit 0,

Solution 1:
You need to put all of them in "@(...)" block.

Solution 2:
always @( a[0] or a[1[] )
begin
b[0] = a[0];
b[1] = a[1];
end

Solution 3:
always @( a[0] or a[1[] )
begin
b = { a[1], a[0] };
end

Some of them may be not 100% correct, but I just want to give you some possible solution.

--Abner--

joe2moon

Joined: 19 Apr 2002
Posts: 389
Helped: 12
Location: MOON

22 Jul 2003 4:25 Verilog Syntax

> always @(a[0] or a[1])
> begin
> b = a ;
> end

OR may just write, ( For a[1:0] and b[1:0] )
always @(a)
begin
b=a;
end
[Tool will check the length of the variables a and b anyway...]

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22 Jul 2003 4:25 Ads

visualart

Joined: 21 Dec 2001
Posts: 588
Helped: 26

22 Jul 2003 10:01

Oh, Thx all.
My code as follow:
reg [10:0] a[3:0];
reg [1:0] b;
reg [15:0] c;
.
.
.
always @(a[0] or a[1] or a[2] or a [3])
reg [1:0] x;
begin x = b;
case( x)
.
.
.
default: c = {4'b0, a[x]} ;
endcase

when I compile, It infor me above information(HDL-180).
Why？
How can I revise it?
Tia