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vonzhaoqun
Joined: 17 Jan 2003
Posts: 24
Location: china
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 18 Jul 2003 6:22 how to design a 74HC245 using verilog? |
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i try many times,but not sucess.  can you help me? thanks
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papyaki
Joined: 13 Apr 2002
Posts: 564
Helped: 19
Location: A small village somewhere in Gaul
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| 18 Jul 2003 7:01 |
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Hi,
Here is alot of standard 74xxx models, but i do not try any :
http://www.eda.org/fmf/fmf_public_models/std/
Here is tutorial from Actel with lot of examples :
http://www.actel.com/documents/hdlcode.pdf
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gauiver
Joined: 10 May 2003
Posts: 102
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| 18 Jul 2003 7:31 |
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i think the program should be like this
assign output=control?input:Z;
if u wanna use output enable then make it
assign output=(control & OE)?input:Z;
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vonzhaoqun
Joined: 17 Jan 2003
Posts: 24
Location: china
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| 18 Jul 2003 11:34 |
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papyaki:
thank you very much!
gauiver:
it is most like a 74hc244,but thank u
any good idea are welcome
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Tetra
Joined: 19 Jun 2003
Posts: 16
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| 20 Jul 2003 8:19 |
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| if you target actual design, you can instantiate Tri-state buffer from the target FPGA and do the required connection. I see a lot of xilinx application do so and do not use HDL description. to avoid different synthesizer methodology.
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vonzhaoqun
Joined: 17 Jan 2003
Posts: 24
Location: china
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| 21 Jul 2003 23:18 |
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Tetra:
thank u,when i try it in vhdl,i got the right result,but i still can not do it in verilog,can u say more about "avoid different synthesizer methodology"?
vonzhaoqun
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