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Tetra
Joined: 19 Jun 2003
Posts: 16
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 17 Jul 2003 12:47 Delay configuration completion by DLL |
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| I read in xilinx data sheets that I can delay the configuration of the FPGA until an internal DLL reach lock state how can I do that.
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zape
Joined: 10 Jul 2003
Posts: 104
Helped: 9
Location: Spain
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| 17 Jul 2003 15:39 |
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| DLL macros have an external pin labeled "LOCKED". This pin shall remain in a low state until the dll generated clocks are stable (frequency and duty cycle).
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Tetra
Joined: 19 Jun 2003
Posts: 16
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| 17 Jul 2003 15:57 |
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| I know that, so should I tie this pin to external output pin and control the ~INT pin to delay the DONE signal ?, or there is an internal methode ?
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zape
Joined: 10 Jul 2003
Posts: 104
Helped: 9
Location: Spain
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| 18 Jul 2003 11:09 |
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| Sorry, I believe I didnīt understand you. If you want DONE pin to be high after DLL locks, you have a checkbox for that in the options for the program file generation (I belive it is in the Startup section).
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