ttspice
Joined: 24 Dec 2001
Posts: 93
Location: Republic of Taiwan
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 10 Jul 2003 3:53 A sample DC tcl script using DC-Ultra |
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A nice article from S*lveNet :
###############################################
#This is a sample DC tcl script that can be used in a top-down or
#bottom-up flows on a block/module level synthesis. This script may
#not always achieve the best possible QOR as some of the variable
#usages are quite design specific.
#
#This script should give you a good quality out-of-the-box QOR for
#aggressive timing/area requirements. Please modify/update the
#script to accomodate your environment setup and design goals.
###############################################
set run tim_area_qor
set TOP_DESIGN my_design
#please fill in the appropriate search path and lib/rtl usage
set MY_SOURCE path_to_source
set search_path [concat [list [format "%s%s" $MY_SOURCE]] $search_path]
set CELL_LIB_DIR path_to_lib
set RAM_LIB_DIR path_to_RAM
set search_path [concat [list $CELL_LIB_DIR $RAM_LIB_DIR] $search_path]
set target_library [list my_tech_lib.db]
set link_library [list my_link_lib.db]
set synthetic_library [list dw_foundation.sldb]
set link_path [concat [concat [concat [list * standard.sldb] $target_library] $link_library] $synthetic_library]
#read design
read_verilog *.v
current_design $TOP_DESIGN
link
#source top(block/module) level constraints(clocks, input/output delay etc.)
source -echo -verbose ../top.cons
source -echo -verbose ../false_paths.cons
set_wire_load_model -name "realistic_WLM" -library "my_tech_lib"
set_wire_load_mode "top"
#compile flow
current_design $TOP_DESIGN
#Please refere to the man pages for details on command usage
#you can vary effort levels depending upon your design goals and results analysis
set dw_prefer_mc_inside true
set hlo_resource_allocation area_only
set hlo_resource_implementation area_only
set compile_seqmap_synchronous_extraction true
set compile_sequential_area_recovery true
set compile_new_boolean_structure true
set_structure true -boolean true -boolean_effort high -timing false
#Enable Design Compiler Ultra optimizations
set_ultra_optimization true
set_boundary_optimization $TOP_DESIGN
set_max_area 0 -ignore_tns
uniquify
compile -map_effort med -area_effort high
report_timing
report_area
compile -incr -map_effort high
report_timing
report_area
ungroup -all -flatten
compile -incr -map_effort high
report_timing
report_area
write -h -o $run.dc.db
exit
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