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madmax
Joined: 10 Jan 2003
Posts: 12
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 28 Jun 2003 16:15 FPGA Design |
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Hi ,
I'm somewhat comfortable in the frontend part of FPGA design , but I'm lagging in the implementation level. Can anyone help me by giving some good materials regarding, tips to place and route , floor plan efficiently in FPGA, Also the issues in FPGA design.
Thanks in Advance
Max
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juripero
Joined: 30 Jul 2002
Posts: 96
Helped: 3
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| 29 Jun 2003 2:36 |
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| If you have synplify or @mplify, they have very good tutorial on the place & route for FPGA included in the user manual
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sanjay
Joined: 04 Jul 2003
Posts: 117
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| 05 Jul 2003 11:00 |
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Hi there,
Yes you can do one thing.
visit www.xilinx.com
and then over there search for Design Flow
In the results given open the page for Design Flow.
There you can find information about design implementation and others as well.
Blv me its brilliant..
Cheers
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stanchen
Joined: 17 Jul 2003
Posts: 5
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| 17 Jul 2003 10:36 Re: FPGA Design |
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| madmax wrote: |
Hi ,
I'm somewhat comfortable in the frontend part of FPGA design , but I'm lagging in the implementation level. Can anyone help me by giving some good materials regarding, tips to place and route , floor plan efficiently in FPGA, Also the issues in FPGA design.
Thanks in Advance
Max |
if the timing issue is not so concerned (you can easily meet the timing constraints of your design)... you can just let the tools do all the job...(synthesis -> synplify pro, P&R -> ISE) Almost automatic!
if the timing is pretty tied or fails to meet the requirements, there's few instructions suggested:
1. re-examine your design, try to eliminate all the critical paths...
2. synthesis with more "decent" constraints (neither over-constrainted nor under-constrainted)
3. put P&R effort to tools' limit...(it's likely to take much more time)
manual floor plan in FPGA is not so suggested except you do know the hardware architecture of FPGA & your design very well...and really know what you're doin'...
regards,
stan
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