electronics forum

Rules | Recent posts | topic RSS | Search | Register  | Log in

FPGA Design


Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> FPGA Design
Author Message
madmax



Joined: 10 Jan 2003
Posts: 12


Post28 Jun 2003 16:15   

FPGA Design


Hi ,

I'm somewhat comfortable in the frontend part of FPGA design , but I'm lagging in the implementation level. Can anyone help me by giving some good materials regarding, tips to place and route , floor plan efficiently in FPGA, Also the issues in FPGA design.

Thanks in Advance

Max
Back to top
Google
AdSense
Google Adsense




Post28 Jun 2003 16:15   

Ads




Back to top
juripero



Joined: 30 Jul 2002
Posts: 102
Helped: 3


Post29 Jun 2003 2:36   


If you have synplify or @mplify, they have very good tutorial on the place & route for FPGA included in the user manual
Back to top
sanjay



Joined: 04 Jul 2003
Posts: 117


Post05 Jul 2003 11:00   


Hi there,

Yes you can do one thing.
visit www.xilinx.com
and then over there search for Design Flow
In the results given open the page for Design Flow.
There you can find information about design implementation and others as well.

Blv me its brilliant..

Cheers
Back to top
stanchen



Joined: 17 Jul 2003
Posts: 5


Post17 Jul 2003 10:36   

Re: FPGA Design


madmax wrote:
Hi ,

I'm somewhat comfortable in the frontend part of FPGA design , but I'm lagging in the implementation level. Can anyone help me by giving some good materials regarding, tips to place and route , floor plan efficiently in FPGA, Also the issues in FPGA design.

Thanks in Advance

Max


if the timing issue is not so concerned (you can easily meet the timing constraints of your design)... you can just let the tools do all the job...(synthesis -> synplify pro, P&R -> ISE) Almost automatic!
if the timing is pretty tied or fails to meet the requirements, there's few instructions suggested:

1. re-examine your design, try to eliminate all the critical paths...
2. synthesis with more "decent" constraints (neither over-constrainted nor under-constrainted)
3. put P&R effort to tools' limit...(it's likely to take much more time)

manual floor plan in FPGA is not so suggested except you do know the hardware architecture of FPGA & your design very well...and really know what you're doin'...

regards,
stan
Back to top
Arabic versionBulgarian versionCatalan versionCzech versionDanish versionGerman versionGreek versionEnglish versionSpanish versionFinnish versionFrench versionHindi versionCroatian versionIndonesian versionItalian versionHebrew versionJapanese versionKorean versionLithuanian versionLatvian versionDutch versionNorwegian versionPolish versionPortuguese versionRomanian versionRussian versionSlovak versionSlovenian versionSerbian versionSwedish versionTagalog versionUkrainian versionVietnamese versionChinese version
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> FPGA Design
Page 1 of 1 All times are GMT + 1 Hour
Similar topics:
What are the FPGA design and FPGA verification? (3)
The major difference between ASIC design and FPGA design! (7)
Good FPGA design Language: Celoxica Handel-C, design suite. (2)
Difference of process between FPGA design and ASIC design (7)
We offer Schematic design, PCB layout & FPGA design (1)
please send me asic design flow and fpga design flow (2)
FPGA design (33)
FPGA design (1)
fpga design (9)
fpga design (2)


Abuse || Administrator || Moderators || Support us || sitemap
topic RSS