Rules | Recent posts | topic RSS | Search | Register  | Log in

How to use the VHDL to design a PLL for CPLD?

 
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital)
Author Message
GoodMan



Joined: 30 Sep 2002
Posts: 369


Post24 Jun 2003 9:49   How to use the VHDL to design a PLL for CPLD?

Hi,

Who can tell me about this design?
Crying or Very sad

3x Embarassed
Back to top
computer_terminator



Joined: 28 Aug 2001
Posts: 72


Post29 Jun 2003 4:13   

You'd better descript your question more detail.
If you want to design an all-digital-pll, you can reference the book wrote by "Best"
Back to top
arena_yang



Joined: 01 Apr 2003
Posts: 36


Post02 Jul 2003 9:16   

Please search DPLL,DLL,PLL in the forum
Back to top
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital)
Page 1 of 1 All times are GMT + 1 Hour


Abuse
Administrator
Moderators
topic RSS 
sitemap