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ukapil
Joined: 23 Jan 2002
Posts: 48
Helped: 1
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 07 May 2003 7:10 Instantiating a component in ISE |
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Hi,
In @ltera we instantiate a PLL, LVDS tx rx block using Megawizard Plugin Manager.
How i do it in Xilinx ISE ?
Also please tell me what is better Stratix or Virtex II pro ?
regards,
Kapil
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leon
Joined: 20 May 2003
Posts: 17
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| 23 May 2003 6:38 |
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Xilinx provides CoreGen.
It has same fuction as MegaWizard in qu(at)rtus.
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leon
Joined: 20 May 2003
Posts: 17
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| 23 May 2003 6:45 |
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In my option, the Xilinx provide better document and more fast device than @ltera. But it is also more expensive that @ltera's device.
Both Stratix and V2p can fill the reqirment in application.
The difference in speed only need to be taken care of when your chip usage is very high.
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Sobakava
Joined: 27 Mar 2002
Posts: 360
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| 20 Nov 2003 15:47 |
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| where can I download cOregen? Is it possible to use it with Webpack 6?
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Sobakava
Joined: 27 Mar 2002
Posts: 360
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| 21 Nov 2003 13:12 |
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I am new to x|linx.
Isn't it synthesisable for webp(at)ck? :
module toplevel(pixel_clock,pixel_counter);
input pixel_clock;
output [11:0] pixel_counter;
reg [11:0] pixel_counter;
always @(posedge pixel_clock)
begin
// this is not working
pixel_counter=pixel_counter+1;
// this is working
pixel_counter=325;
end
endmodule
Can't I increment a reg? I was doing this with M(at)X plus of @lter@. I use M0delsim for simulation and pixel_counter looks Hi-Z/undefined at simulation. What do I have to do?
Is there a step-by-step beginner to advanced book/ebook for X|linx I5E?
Regards
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karlheinz
Joined: 09 Feb 2003
Posts: 35
Helped: 1
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| 21 Nov 2003 17:31 Re: Instantiating a component in ISE |
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try this:
module top_level (pixel_clock, pixel_counter, reset);
input pixel_clock;
wire pixel_clock;
output [11:0] pixel_counter;
reg [11:0] pixel_counter;
input reset;
wire reset;
always
@( posedge pixel_clock or posedge reset )
begin
if (reset)
pixel_counter <= 0;
else
pixel_counter <= pixel_counter + 1;
end
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massive
Joined: 20 Jul 2003
Posts: 46
Location: Sofia, Bulgaria
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| 21 Nov 2003 18:11 Re: Instantiating a component in ISE |
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try this code:
| Code: |
module toplevel(pixel_clock,pixel_counter);
input pixel_clock;
output [11:0] pixel_counter;
reg [11:0] pixel_counter = 0;
always @(posedge pixel_clock)
begin
pixel_counter=pixel_counter+1;
end
endmodule
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it is better to inser a reset condition like in previous example..
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