Rules | Recent posts | topic RSS | Search | Register  | Log in

Virtuoso - Export GDSII

 
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital)
Author Message
elektor



Joined: 19 Mar 2002
Posts: 67
Helped: 1


Post15 Apr 2003 12:51   Virtuoso - Export GDSII

Hi,

I use GDSII file from Silicon Ensemble. Now I know that this GDSII it is "layout does not include standard cells".
When I've put this file in Cadence CIW ( Import - Stream ) I've obtained warning : " (setup file ) - scale was not float " and nothing else.

I've tested a lot of possibilites ( UU/DBU ) - No effect..

Regards
Elektor

PS. When I've put DEF file from SE everything was ok, but when I've tried Export Stream , problem has come back ....

PS. Main obiective : Put "full" GDSII to Calibre DRC, because GDSII from SE doesn't work.
Back to top
napong



Joined: 06 Jan 2002
Posts: 36


Post16 Apr 2003 2:36   

Before importing, you should have standard cells layout in CIW that have name correspond to you LEF in SE.
When you Import->Stream, add option retain library definition.
This option will search the cell name in CIW that match with the cell name from SE and use that cell in CIW as a standard cell.
Hope it could solve your problem.
napong.
Back to top
ttspice



Joined: 24 Dec 2001
Posts: 93
Location: Republic of Taiwan


Post16 Apr 2003 13:55   

I think SE only exports metal, via and cell outline....


# example of SE script
# gds2 out
#
OUTPUT GDSII MAPFILE "gds2.map" LIBNAME "top" STRUCTURENAME "top" FILE "top.gds" REPORTFILE "gds2out.jnl" UNITS Thousands ;


Just make sure your mapfile and units are correct, then import the gds
with standard cell libary as well.


# example of GDS map
#
# Silicon Ensemble 5.X Stream layer mapping table
#-----------------------------------------------------------------------------
#gds layer SE layer Layer object type
#==================================

15 CONT VIA;
16 METAL1 NET;
16 METAL1 VIA;
16 METAL1 SPNET;
17 VIA12 VIA;
18 METAL2 NET;
18 METAL2 VIA;
18 METAL2 SPNET;
27 VIA23 VIA;
28 METAL3 NET;
28 METAL3 VIA;
28 METAL3 SPNET;
62 NAME CELL ;
29 VIA34 VIA;
31 METAL4 NET;
31 METAL4 VIA;
31 METAL4 SPNET;'
32 VIA45 VIA;
33 METAL5 NET;
33 METAL5 VIA;
33 METAL5 SPNET;'
39 VIA56 VIA;
38 METAL6 NET;
38 METAL6 VIA;
38 METAL6 SPNET;'
21 VIA67 VIA;
22 METAL7 NET;
22 METAL7 VIA;
22 METAL7 SPNET;'
Back to top
siboy



Joined: 23 Apr 2006
Posts: 56


Post23 Jun 2006 16:36   Virtuoso - Export GDSII

What's the meaning of "via""net""spnet" after each metal layer?
Thanks!
Back to top
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital)
Page 1 of 1 All times are GMT + 1 Hour


Abuse
Administrator
Moderators
topic RSS 
sitemap