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how to verify a 32-bit full adder with testbench
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ASIC Design Methodologies & Tools (Digital)
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wildpig
Joined: 18 Mar 2003
Posts: 2
18 Mar 2003 11:37
how to verify a 32-bit full adder with testbench
as the title
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rfsystem
Joined: 25 Feb 2002
Posts: 778
Helped:
83
19 Mar 2003 0:49
If the full adder is
A+B+CIN->S+COUT
set A=FFFFh and B=0000h and CIN=1b
and interchange A and B. With this test you trigger the critical path. Toggling all nodes with a reduced vector set require knowledge about the implementation.
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