eda_wiz
Joined: 07 Nov 2001
Posts: 717
Helped: 30
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 17 Mar 2003 12:34 Design Doubt |
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Q. Design a logic which mimics a infinite width register. It takes input serially 1 bit at a time. Output is asserted high when this register holds a value which is divisible by 5.
For example:
Input Sequence Value Output
1 1 1 0
0 10 2 0
1 101 5 1
0 1010 10 1
1 10101 21 0
Using an FSM to create this
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