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dd2001
Joined: 14 Apr 2002
Posts: 282
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 14 Mar 2003 20:13 IIP3 issue? |
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| Design a CMOS LNA, got IIP3=1.5dBm, Which don't meet the requirement? Anyone know how to improve IIP3?
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VSWR
Joined: 07 Feb 2002
Posts: 639
Helped: 53
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| 14 Mar 2003 21:01 Re: IIP3 issue? |
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You have to be more specific. What frequency? What transistors are used? At what bias (drain voltage and drain current if a FET or GaAs FET is used).
In some cases increasing the drain current for a FET may improve IIP3, but then noise figure can be degraded.
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nathan
Joined: 17 May 2001
Posts: 307
Helped: 2
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| 14 Mar 2003 22:23 |
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Make it differential, increase Vsg-Vt, moderate your gain ... as simple as it is 
nathan
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byron
Joined: 25 Jan 2002
Posts: 106
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| 15 Mar 2003 3:41 |
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| the most common method is to use feedback, for example using inductor, resistor or capacitor as emitter(or source) degeneration. of course increasing current is a method. however, it all depends on your circuits and your requriements, especially other specs. There are tradeoffs betwenen linearity, noise and gain.
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