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kinysh
Joined: 16 Jul 2002
Posts: 67
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 13 Mar 2003 5:25 pll skip clock |
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we are using a pll on chip.
input 12M, output 96Mhz, we divide it by 4 and output to the pad,
when we monitor the pad,
sometimes the logic analyzier will display a min frequcecy of 12Mhz.
it takes about 1-2 minutes.
how could this happen in a pll design.
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flatulent
Joined: 19 Jul 2002
Posts: 4860
Helped: 288
Location: Middle Earth
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| 13 Mar 2003 7:28 instrumentation problem? |
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| It could be an instrumentation problem caused by your logic analyzer. Try examining the pad with a digital storage scope and look for unexpected voltage levels and pulse widths. The newer Tektronix scopes can be set to trigger on undersized or oversized pulses.
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kinysh
Joined: 16 Jul 2002
Posts: 67
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| 14 Mar 2003 7:12 |
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yes, I also doubt that, I will try it figure that out tomorrow.
but what strange is at measure a 45Mhz output is better than a 22.5Mhz.
I monitore 45Mhz severial minutes, not problem.
22.5Mhz will have probelm easily in the same period.
bests
kinysh
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Nobody
Joined: 04 Oct 2001
Posts: 250
Location: Formosa
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| 14 Mar 2003 17:44 |
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| some AMP gain in your circuit get too high in low frequency range and result in spurious oscilation .
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kinysh
Joined: 16 Jul 2002
Posts: 67
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| 15 Mar 2003 1:25 |
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Thanks, all
the stupid scope make the mistake.
but after that, I still find some bit pll jitter, about >1 ns
bests
qysheng
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