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[REQ] - experience with FPGA with built in SerDes


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kobik



Joined: 24 Sep 2002
Posts: 63


Post12 Mar 2003 17:34   

[REQ] - experience with FPGA with built in SerDes


Shocked

on PCB or/and cable
Altera or Xilinx

tia Very Happy
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juripero



Joined: 30 Jul 2002
Posts: 102
Helped: 3


Post12 Mar 2003 18:25   


What do you want to know? signal integrity? pcb design guide?
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kobik



Joined: 24 Sep 2002
Posts: 63


Post13 Mar 2003 7:47   


hi,

thx for the fast replay

i want to know from people experience the FPGA SerDes capability:
1. the PCB length that they success to drive (+frequency)
2. the cable length that they success to drive (+frequency)
3. problem that they experience with

best regards
kobik Wink
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juripero



Joined: 30 Jul 2002
Posts: 102
Helped: 3


Post13 Mar 2003 22:29   


I have been experimenting with Serdes from both @ltera and Xilinx , also some other ASSP vendors. Generally speaking, all these serdes are designed to drive 40 inchs FR4 backplane, and they all meet that spec.

In terms of performace, I think ASSP vendor generally have a better part, for example Broadcom has very strong serdes product.

The serdes performance of @ltera and Xilinx are comparable, I would say.

All the serdes works from 1G - 3.2 Gbps
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maestor



Joined: 21 Feb 2002
Posts: 176
Helped: 1
Location: Espaņa


Post19 Mar 2003 14:21   


Hi,

I was introduced a couple of days ago to the L(at)ttice SerDes devices

h*t*t*p://www.l(at)tticesemi.com/products/fpsc/ort82g5/index.cfm

They looked all right. They have this thing called "pre-emphasis" which could be easily modified in the SerDes and was improving the eye-diagram a lot (with some side effects like an increase in the power consumed...).
They have serial data rates from 0.6 to 3.7 Gbit/s.

I have not experience with SerDes to be honest but just in case this helps,
Regards,

- Maestor
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juripero



Joined: 30 Jul 2002
Posts: 102
Helped: 3


Post19 Mar 2003 18:33   


pre-emphasis is now a common technique used in Serdes products. All the serdes products I have seen have this feature. The pre-emphsis will boost high frequency part of the signal, thus make the signal quality better after it passes through a long transmission line.

some serdes products(like @ltera GX) also have equalizer, which is sitting on the receiver side, it is the same principle as pre-emphasis, it also helps cleaning up the signal.
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Post19 Mar 2003 18:33   

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rx300



Joined: 02 Mar 2002
Posts: 61


Post23 Mar 2003 4:40   


maestor wrote:
Hi,

I was introduced a couple of days ago to the L(at)ttice SerDes devices

h*t*t*p://www.l(at)tticesemi.com/products/fpsc/ort82g5/index.cfm

They looked all right. They have this thing called "pre-emphasis" which could be easily modified in the SerDes and was improving the eye-diagram a lot (with some side effects like an increase in the power consumed...).
They have serial data rates from 0.6 to 3.7 Gbit/s.

I have not experience with SerDes to be honest but just in case this helps,
Regards,

- Maestor



Lattice never had any expertise in SerDes. Lattice never designed any SerDes. But now they have the SerDes in their products. How? It all came from the 250 mil purchase of Orca FPGA. They also obtained access to Agere's state-of-art SerDes technology. Presumably, Lattice will always get SerDes technology for free from Agere. That 250 mil sure got a lot for them.

I know Agere's SerDes technology has been pretty good. So, Lattice's counterpart should be good too.

rx300
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grigodedes



Joined: 06 Mar 2008
Posts: 4


Post01 Apr 2008 22:23   

Re: [REQ] - experience with FPGA with built in SerDes


Hi,

back to 2003, 3.2 Gbps were ok but what about now?

Has anybody actually experienced over 5 Gbps with latest fpgas?

Best Regards
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Zerox100



Joined: 01 Mar 2003
Posts: 327
Helped: 10


Post02 Apr 2008 7:19   

Re: [REQ] - experience with FPGA with built in SerDes


I think with rapiodIO technology talking about serdes is wasting time!!
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grigodedes



Joined: 06 Mar 2008
Posts: 4


Post02 Apr 2008 9:14   

Re: [REQ] - experience with FPGA with built in SerDes


What are the capabilities of the RapidIO technology?
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