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fangll
Joined: 11 Sep 2002
Posts: 25
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 03 Mar 2003 9:18 How to generate the testbench for signal process algorithim? |
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I want to generate plenty of data as stimulation to simulate the digital receiver design usued verilog. how to generate the modulation data. I know the matlab can do it, but the data file pre-generate can not used for long time simulation because of i need read a very large data file into the testbench routine.
Any one can give me some advice?
thx!
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juripero
Joined: 30 Jul 2002
Posts: 96
Helped: 3
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| 03 Mar 2003 9:53 |
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| Useing simple channel model and write verilog code for it, also write a transmitter verilog model.
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fangll
Joined: 11 Sep 2002
Posts: 25
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| 04 Mar 2003 7:14 |
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| thank juripero, thank for your help. But if i want to add channel model, such as fade, interference, how can i deal with it. The In-build function in verilog simulation is too little.
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juripero
Joined: 30 Jul 2002
Posts: 96
Helped: 3
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| 17 Mar 2003 19:31 |
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| You are right, Verilog is not so convienient in terms of channel modeling and system simulation, that is why Simulink and Systemview are nomally used for that purpose.
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Bogyman
Joined: 19 Aug 2001
Posts: 19
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| 17 Mar 2003 19:58 |
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| Systemview have large channel model lib + related comm sig generators. Can see time/spectrum/BER displays easy.
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ramesh
Joined: 19 Jan 2003
Posts: 1233
Helped: 4
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| 18 Mar 2003 6:05 |
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Also see the VISSIM/COM software
www.vissim.com
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steshenko
Joined: 31 May 2002
Posts: 67
Helped: 1
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| 18 Mar 2003 8:24 |
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| In same case we usualy tes model in C or Systemview and generate files or in best case use real record of input signal. For functional testing you may scale sample ratio (decrease it) and test in generated files
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