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PowerEDA2003
Joined: 06 Feb 2003
Posts: 19
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 01 Mar 2003 12:03 Encrypted Design Files |
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It is possible to encrypt HDL design files for functional simulation. How I can protrct my design during synthesis? I want to give the customer a file, which is synthesizable but its content is not viewable! How I can do it?
Any help?
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mariaR
Joined: 28 Feb 2003
Posts: 200
Helped: 1
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| 01 Mar 2003 22:23 |
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| It's an interesting question ! I've never heard such tool. Anyone know?
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ejean
Joined: 01 Jun 2001
Posts: 28
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| 02 Mar 2003 4:43 |
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| DesinWare can produce BLOCK IP in encrypted format. If you want to provide your source code in encrypted format, you can choose pre-compiler base HDL simulator, these software can compile the original HDL code to it's "native-code". Modelsim, VCS, NC-verilog, SpeedSim, etc. can do this job.
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firendchn
Joined: 11 Sep 2002
Posts: 29
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| 22 Sep 2003 10:23 Re: Encrypted Design Files |
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ejean,
give an example pls!
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