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tryagain
Joined: 14 Jun 2002
Posts: 9
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 25 May 2004 13:47 Re: Digital oscilloscope Project |
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| bitscope is two channel 40MHZ sample,it is use two tlc5540,if you need higher frequency sample,you can use maxim adc to do it.
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abs
Joined: 29 May 2004
Posts: 9
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| 29 May 2004 14:55 Re: Digital oscilloscope Project |
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 hellow every one. I'm comes from China mainland. I'm looking for (and want to join in) a free project to build up lowcost PC scope. for our
Chiness people most of equipment are too expensive to buy,so it's a goold idea to build up one my self, if any one can help? Thanks .
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joc_06
Joined: 28 Nov 2003
Posts: 51
Helped: 2
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| 29 May 2004 16:53 Re: Digital oscilloscope Project |
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| Look at the links posted above especially the chocbar project. I am just beginning to gather parts to build this one so it should be interesting
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eltonjohn
Joined: 22 Feb 2002
Posts: 1558
Helped: 22
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| 29 May 2004 17:10 Re: Digital oscilloscope Project |
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I have a project that i never got to finish.. One of those things .. It's a nice idea .. but too pricy and complex .. it's a scope in a PCMCIA card
i think that i will migrate the whole design to a FPGA .. i was using Ti a DSP and a CPLD(triscend ) for the interface .. but it is too big for the little room !
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abs
Joined: 29 May 2004
Posts: 9
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| 30 May 2004 15:12 Re: Digital oscilloscope Project |
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thanks. I think as an equitment to test radio equipments.high speed (dual channel 80Msps or highter) is more useful for me,tom's design spand too much time on storage depth, may cause high price for one to build up.I think for common use(and for me) 64K storage depth is enough.
In China the cheapest A/D chip is TI ads831e (8BIT 80Msps).If any one has used it? i just want to know if it is realy as good as TI says?
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abs
Joined: 29 May 2004
Posts: 9
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| 31 May 2004 13:56 Re: Digital oscilloscope Project |
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I had read a lot this days.And finally I found MK3 by David Jones is the easyest to buile up PC-based DSO.It is realy a old project,build up by some classic 74HCxx TTL chip,None CPLD even has no MCU.I think it is the right thing I need,one reason is that a basic CPLD chip as @ltera EMP7128S cost about 80Y/8=10$ in China ,it is a large number for me and my friend Li.
But the A/D chip used in MK3 is only works at 20Msps,It is not enough,I want use an ADS831 (TI-BB) instead.Now the disadvantages of FIFO chip become a big problem.I could not find out an FIFO chip who can work on the clock rate of 80M.could any one can help me just to find out something cheap which can works on the high speed normal?thanks!
Or any one has advice for me,do let me know please.
Best Regards.
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monnoliv
Joined: 09 Mar 2004
Posts: 100
Helped: 3
Location: Belgium
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| 31 May 2004 23:46 Re: Digital oscilloscope Project |
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Hi, look here http://www.soudez.org/Page_Projet2.php.
It's a two channels DSO (2x100MS/s with FIFO), I've just finished the schematics. I'm going to do the design of the PCB. The purpose of this project is to have a cheap self powered DSO on USB port. Open source design, comments welcome !
@+,
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tryagain
Joined: 14 Jun 2002
Posts: 9
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| 01 Jun 2004 0:20 Re: Digital oscilloscope Project |
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Dear monnoliv,
I'am in china,I can not enter this site:
http://www.soudez.org/Page_Projet2.php
Why?
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monnoliv
Joined: 09 Mar 2004
Posts: 100
Helped: 3
Location: Belgium
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| 01 Jun 2004 9:48 Re: Digital oscilloscope Project |
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Server was busy, try now ...
A+
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is_razi
Joined: 06 Apr 2002
Posts: 163
Helped: 6
Location: Tabriz
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| 01 Jun 2004 12:38 Re: Digital oscilloscope Project |
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| tryagain wrote: |
| bitscope is two channel 40MHZ sample,it is use two tlc5540,if you need higher frequency sample,you can use maxim adc to do it. |
hi,
do you have cpld's required files.if so please send to me .
regards.
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abs
Joined: 29 May 2004
Posts: 9
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| 01 Jun 2004 13:12 Re: Digital oscilloscope Project |
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 IT seems that I could not visit monnoliv's websit too.I even could not visit www.Bitscope.com from China Mainland.I will try to use a PROXY,I hope that could made something help.
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monnoliv
Joined: 09 Mar 2004
Posts: 100
Helped: 3
Location: Belgium
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Skov
Joined: 15 Mar 2003
Posts: 7
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| 01 Jun 2004 18:31 Re: Digital oscilloscope Project |
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2monnoliv:
Hi,
my oppinion:
1) It is recommended to add pull-up resistors for JTAG.
2) CP2101 is more simple than FTDI
3) The trigger scheme should be implemented in CPLD
I made DSO with almost the same architecture.
EPM3064-7 was not fast enough. I was forced to use
2xEPM3032-4 (one per channel).
My project was not completed.
Time(money) was over ;)
Regards,
S
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jaac
Joined: 12 Mar 2002
Posts: 67
Location: Colombia
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| 01 Jun 2004 22:05 Re: Digital oscilloscope Project |
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What do you have in your mind?
How could we help?
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martingn
Joined: 30 Mar 2004
Posts: 40
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| 01 Jun 2004 22:40 Re: Digital oscilloscope Project |
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Hi All,
Im not an expert but after browse all the DSO projects in the net I came to the following:
- the best option is to replace FIFO+CPLD by a FPGA with internal RAM.
Cheaper ex.@ltera ACEX1K ~100Mhz RAM 3x512bytes U$S12
Faster ...can do trigger
- use a full differential OP at the input of the ADC is better (better noise relation).
Regards,
Martin
PS:(Even although there is not too much info yet, there is a good site with a DSO project not listed in this post http://area26.no-ip.org/?section=hard&project=scope)
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alphi
Joined: 23 Dec 2001
Posts: 439
Helped: 1
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| 02 Jun 2004 0:15 Re: Digital oscilloscope Project |
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| Do you have active link about this project link?
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joc_06
Joined: 28 Nov 2003
Posts: 51
Helped: 2
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| 02 Jun 2004 13:46 Re: Digital oscilloscope Project |
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any english translation for this??
Also fpga's are not difficult to use and are really powerful. check here for a great intro to them
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khach
Joined: 23 Oct 2001
Posts: 48
Helped: 2
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| 02 Jun 2004 15:13 Re: stroboscopic method of the measurement for DSO |
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| Make_Pic wrote: |
| I need any information about a stroboscopic method of the measurement for DSO! The stroboscopic method allows to measure Frequencies up to about 3 GHz. |
RIS (random interval sampling) is good advanteges of scopes. Old HP scopes work with 500 MHz bandwith with 20 Mhz ADC. Its TDC (time to digital converter) based. Analog trigger start TDC then ADC clock stop it. At the TDC out DC voltage is proportional to trigger to clock delay. Low speed ADC convert this voltage to code proportional to delay.
I need information about TDC logic implementation in CPLD. Main problem is complementary design of TDC logic. Any shifts of comlementary clocks signal for high speed diode switch is degrade TDC perfomance. Any suggestion about comlementary sygnal vhdl implementation?
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alphi
Joined: 23 Dec 2001
Posts: 439
Helped: 1
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| 02 Jun 2004 15:41 Re: Digital oscilloscope Project |
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| Hi,everyone known which sample adc chip be used in tek digital oscilloscope:TDS220?
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dainis
Joined: 15 May 2001
Posts: 1453
Helped: 56
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| 02 Jun 2004 21:52 Re: Digital oscilloscope Project |
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| alphi wrote: |
| Hi,everyone known which sample adc chip be used in tek digital oscilloscope:TDS220? |
I have some information, that TDSxxx oscillscopes do not have fast ADC, but for fast sampling it use CCD (charge-coupled device device) device, may be it have different name (not CCD) ....
p.s.
1) TDSxxx scopes is very good for her price !
2) It have very limited channel memory
3) Sampled signal is noisy
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monnoliv
Joined: 09 Mar 2004
Posts: 100
Helped: 3
Location: Belgium
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| 02 Jun 2004 23:56 Re: Digital oscilloscope Project |
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Thank you all of you for your advices.
In particular Skov, just some questions for you:
Why EPM3064-7 wasn't fast enought ?
Why do I use resistor to pull up signals for JTAG (didn't see in the docs)?
For Martingn: I'll try to evaluate your proposal, it seems vgood (I wasn't aware that there exist FPGA with RAM :sm15: and so cheap! ).
| Quote: |
| - use a full differential OP at the input of the ADC is better (better noise relation). |
that's what I did, no?
Thanks joc_26 for your fpga advice, concerning translation of the site, I'll do it one day just for the DSO (waiting for a stable revision of the DSO schematic).
N.B: I've just calculate the budget for the DSO: about 250€ just for the components!
Bye.
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ME
Joined: 14 Mar 2002
Posts: 1771
Helped: 11
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| 03 Jun 2004 0:35 Re: Digital oscilloscope Project |
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| monnoliv wrote: |
Hi, look here http://www.soudez.org/Page_Projet2.php.
It's a two channels DSO (2x100MS/s with FIFO), I've just finished the schematics. I'm going to do the design of the PCB. The purpose of this project is to have a cheap self powered DSO on USB port. Open source design, comments welcome !
@+, |
It looks like a very nice project, but it would be easier to make comments if you translated the site into English.
Not many of us understand French (including me), but we all understand English here at EDAboard.
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martingn
Joined: 30 Mar 2004
Posts: 40
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| 03 Jun 2004 4:34 Digital oscilloscope Project |
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Hi all,
Monnoliv, take a look at the cheapest FPGA @ltera has with RAM included.ACEX 1K EP1K10 (3x512bytes)
You can find a nice project at http://fpga4fun.com that uses this chip including some trigger code.
Hopelly I will start a prototype soon...
Best regards,
Martin
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Skov
Joined: 15 Mar 2003
Posts: 7
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| 03 Jun 2004 6:42 Re: Digital oscilloscope Project |
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Hi,
>>Skov, just some questions for you:
>>Why EPM3064-7 wasn't fast enough?
Did you write firmware for this project and check it in simulator?
Why do you think that EPM3064-7 is enough?
I think it depends on tasks for CPLD.
My project was fully completed and simulated
in the part of verilog program for CPLD.
The tasks for CPLD were the communication with outer FIFO, MCU, ADC,
settings for pre-history storage size, trigger levels and polarity,
mutual synchronization of the both channels and many others.
For my tasks EPM3064-7 was not enough fast.
>>Why do I use resistor to pull up signals for JTAG (didn't see in the
>> docs)?
There are a lot of docs on @ltera’s site ;)
See docs on ByteBlaster.
About memory size.
I think the memory 3x512bytes is not enough.
For example, DSO from Tek has 3.5KB memory.
Other DSOs have 100KB memory and more.
Regards,
S
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pisoiu
Joined: 31 Dec 2002
Posts: 889
Helped: 24
Location: Romania
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| 03 Jun 2004 7:11 Re: Digital oscilloscope Project |
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| alphi wrote: |
| Hi,everyone known which sample adc chip be used in tek digital oscilloscope:TDS220? |
I have opened a TDS2014 (4 channel 1gsps) to see what's inside. They use a pair of chips for every pair of channels. It seem that one chip is amplifier and sampling , and the other one fifo. The input section does not have many components around, all are passive. The only active one seem to be an ac/dc optomos switch. Anyway, the chips are proprietary designs, manufactured by National. Not even a single bit on information about them on the net. I've attached a pic with them.
/pisoiu
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se06745
Joined: 03 Jun 2004
Posts: 26
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| 03 Jun 2004 9:33 Re: Digital oscilloscope Project |
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Hi!
Why all oscilloscopes are limited +5v -5v ???
The original don't have these low voltage limit.
thanks
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pisoiu
Joined: 31 Dec 2002
Posts: 889
Helped: 24
Location: Romania
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| 03 Jun 2004 9:48 Re: Digital oscilloscope Project |
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I assume you are talking about voltage input limits. Not all have this limitations, but high performance ones have. This is because high performance oscilloscopes have extremely wide input bandwith. In order to achieve this and a good linearity over entire freq. range, the input amplifier must have low input capacitance. High voltage protection circuits, up to hundreds of volts add undesired capacitance to the input. And besides that, it is unpractical. If you spend a lot of money on a 1ghz bandwidth DSO, mostly you'll measure high freq. signals, which are low voltage rather than what is on the mains. For higher voltages, 1:10 or higher rate divider probes are available anyway.
/pisoiu
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Skov
Joined: 15 Mar 2003
Posts: 7
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| 03 Jun 2004 10:13 Re: Digital oscilloscope Project |
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Usually, the input chain of oscilloscopes has low resistance (50..150 Ohm) in accordance with low impedance of cable
which is connected to oscilloscope. The dissipated power for input chain is limited.
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monnoliv
Joined: 09 Mar 2004
Posts: 100
Helped: 3
Location: Belgium
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| 03 Jun 2004 14:23 Re: Digital oscilloscope Project |
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Skov ??? I've seen on several DSO 1Meg of input impedance.
martingn, Concerning the ACEX 1K EP1KX0, if I've well understand the strucure of this device, it must be configured at each power on. How doing this with embedded processor, EEPROM? Do you have a schematics ?
Regards,
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ME
Joined: 14 Mar 2002
Posts: 1771
Helped: 11
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| 03 Jun 2004 14:41 Re: Digital oscilloscope Project |
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| Skov wrote: |
Usually, the input chain of oscilloscopes has low resistance (50..150 Ohm) in accordance with low impedance of cable
which is connected to oscilloscope. The dissipated power for input chain is limited. |
That is not true, normally the input impedance of oscilloscopes is 1 MΩ || ~10-100 pF.
Using 1:10 probes, the input impedance is 10 MΩ and the capitance is lower than with 1:1 probes, with 1:100 probes, the input impedance is 100 MΩ and the capitance is even lower than for 1:10 probes.
DSO's like Tektronix TDS 1000 & TDS 2000 series for example has an input impedance of 1 MΩ || 20 pF.
If you were interested in trasferring maximum power you should use low impedances for impedance matching, but with oscilloscopes and voltmetres you are only interested in transferring maixmum voltage, whitout drawing any current from the source, so the input impedance is usally >= 1 MΩ.
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