EricGuo
Joined: 15 Jan 2003
Posts: 10
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 24 Jan 2003 3:30 problem after postmap simulation |
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Hi,all
I use xilinx ISE and modelsim to design a project . Although the final output is like what i wanted , I get a error indication in modelsim consol after postmap simulation as following :
Error: d:/Xilinx/verilog/src/simprims/X_LATCHE.v(64): $width( posedge CLK:9939316 ps, :9939656 ps, 1400 ps );
can anyone explain this error message to me ? thank you in advance !
pls. can I write a constrain condition for LATCH in the xilinx ISE? IF can, How to ?  [/img]
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gnomix
Joined: 14 Jun 2001
Posts: 137
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| 24 Jan 2003 9:25 Re: problem after postmap simulation |
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| EricGuo wrote: |
Hi,all
I use xilinx ISE and modelsim to design a project . Although the final output is like what i wanted , I get a error indication in modelsim consol after postmap simulation as following :
Error: d:/Xilinx/verilog/src/simprims/X_LATCHE.v(64): $width( posedge CLK:9939316 ps, :9939656 ps, 1400 ps );
can anyone explain this error message to me ? thank you in advance !
pls. can I write a constrain condition for LATCH in the xilinx ISE? IF can, How to ? [/img] |
Hi,
I'm not sure but from this message seem that you have a 340ps spike on the enable signal.
The 1400ps is the minimum required pulse width for a valid condition on this pin.
rgs
gnomix
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