ted
Joined: 12 Mar 2002
Posts: 118
Helped: 3
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 24 Jan 2003 1:12 Developing FPGA with Leonardo Spectrum and @ltera MAX II+ |
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I am working with a VHDL project where the tools are the free versions of: Leonardo Spectrum (@ltera edition) and MAX II + 10.12, while the chip is ACEX1k50. Design is small enough to fit very easily, but has some tough timing requirements.
Actually the tools are not too bad, at least up to a certain point. But a misery starts when fitting the result. The placement generated by fitter(e) in MAX II+ is horrible. Selecting "optimize for speed" in Leonardo helps very little, the horror is in routing. And that is done by MAX II +, which has two fittere: One old and pretty bad (spreading cells all over like a shotgun), another is using "qu(at)rtus technology"--it's a little better but has restrictions in assignements it accepts. And still not smart enough for good, timing optimal placement.
OK, I can use the floor plan editor and manually improve the result -- but then, I have two issues:
1) The compilation by Leonardo renames internal nets in a module very often to some auto-generated ones, so that finding anything in the design is made maximally difficult. How to prevent that grazy renaming of stuff?
2) When I have for instance a critical setup time issue from a certain pin to a certain register, finding which path is the slowest is not easy. At least I have not yet found out how to find that in MAX II +
Have anybody experiences with the package, and could help me with these two issues?
Ted
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TurboPC
Joined: 14 Mar 2002
Posts: 148
Helped: 1
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| 24 Jan 2003 3:03 |
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Hi,
I don't have all the answers, but here some thoughts:
1a) Have you tried to create 'clique' for some module? There is surely an attribute in Leonardo. In MAX+, you can assign a clique to a certain position in the device.
1b) You can also use qu(at)rtus and use the "logic lock" function to lock sub-modules at absolute or relative position within the device.
2a) In MAX+, open the "Timing Analyser" window and start the "Registered Performance" analyser. You can list slowest net by cliking 'Show Path". You'll get a list of nets with all the names from your VHDL hiearchy.
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