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What is your way to stop a VHDL simulation?
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pini_1



Joined: 18 Jun 2007
Posts: 288
Helped: 17
Post07 Nov 2009 9:07   

What is your way to stop a VHDL simulation?
I use the assert … report … severity statement.
Example
http://bknpk.no-ip.biz/my_web/MiscellaneousHW/vhdl_stop_on_error.html

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Post new topic  Reply to topic    EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> What is your way to stop a VHDL simulation?
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