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digital asic design flow. flow is better? why?
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cosmosd



Joined: 30 Mar 2009
Posts: 2
Post06 Nov 2009 10:54   

digital asic design flow
hi we are desiging a small digital system that include a cpu ,and two IPs with AHB bus, i am a little confused about the design flow:some one said i should synthesis the whole design in the DC , and some one told me that i should partition my design in the SOC ENCOUNTER, and then desgin the blocks separately. so I want to ask which flow is better? why? Thanks.
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pini_1



Joined: 18 Jun 2007
Posts: 288
Helped: 17
Post06 Nov 2009 19:55   

Re: digital asic design flow
I think that dividing your design to smaller blocks always help. You can than simulate first in block level and have small running time. The smaller blocks are re-useable for other projects.
As for the synthesis it depends how big your design is. If it is not too large, than do a top down synthesis flow, which is the easiest. Some complex design require bottom top.

Here are some examples from my site that may help:
Since you mentioned AHB:
"The following will show a simple AHB monitor. The monitor can be applied to any AHB bus to debug the activity of the bus...."
http://bknpk.no-ip.biz/my_web/AHB_MON/ahb_mon_1.html

Digital Design General:
http://bknpk.no-ip.biz/my_web/ComplexMultiplier/CM_1.html
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Post06 Nov 2009 19:55   

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ljxpjpjljx



Joined: 05 May 2008
Posts: 532
Helped: 12
Location: Shang Hai
Post07 Nov 2009 4:15   

Re: digital asic design flow
first your IP should be verified in UVE ! Then do a top level synthesis and run fullchip simulation!
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Syswip



Joined: 11 Nov 2009
Posts: 13
Helped: 2
Post13 Nov 2009 13:59   

Re: digital asic design flow. flow is better? why?
Hi cosmosd,

If your design is less then (... lets say) 200k gates and you don't have any black box in your design then use top down flow. It is really easy.


Quote:

first your IP should be verified in UVE !


ljxpjpjljx could you please tell me what is it?

Thanks

Tiksan,
http://syswip.com/
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