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Xilinx 7.1i version "Cannot synthesis operator DIV"
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sunky



Joined: 06 Nov 2009
Posts: 1
Post06 Nov 2009 8:36   

need help, please
hello friends, i am a beginner in VERILOG, my project is based on calculating modular multiplication value (Z=X*Y mod M).
It needs the div operator / to calculate the quotient value.
I am working in Xilinx 7.1i version.
While synthesis it gives the following error "Cannot synthesis operator DIV"
Anyone, please help me in fixing this error.
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muni123



Joined: 28 Apr 2007
Posts: 19
Helped: 1
Location: India
Post06 Nov 2009 12:59   

Re: need help, please
Hi Sunky,

The best way we can make this work is to move on to the latest version of Xilinx ISE.
Xilinx ISE 9.1i supports DIV operator to my knowledge. Please check.

Thanks!!
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