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spartan II block ram problem
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thepiper



Joined: 25 Sep 2008
Posts: 7
Post05 Nov 2009 11:18   

spartan II block ram problem
hi, i have implemented a design on an spartan ii fpga, and it includes a block ram which is read on every clock cycle by an incrementing address, but i found out it just fails on certain addresses and reads a data from an adjacent address, i don't think it's a clock related problem and post p&r simulation works just fine, that's why i'm confused and need help! what could be the problem?
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