Relation b/w Timing parameter(Tcq) & PVT(Process,Volt.,T

EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> Relation b/w Timing parameter(Tcq) & PVT(Process,Volt.,T

Author

Message

vikram789

Joined: 01 Aug 2008
Posts: 36

05 Nov 2009 5:03 Relation b/w Timing parameter(Tcq) & PVT(Process,Volt.,T

hi, i simulated an instance over 4 PVT(Process,Voltage.Temparature) to observe the relation between Timing parameter(Tcq) and PVT

4PVT are
1.ffqb0p99vn40c
2.ffqb0p99v125c
3.ssqb0p81vn40c
4.ssqb0p81v125c

I observed follwing results which seem to be contradicting
ffqb0p99vn40c| ffqb0p99v125c| ssqb0p81vn40c| ssqb0p81v125c
Tcq -> 0.397 |0.464 |1.176 |1.086

Can anyone me by explaining this trend ...

koggestone

Joined: 16 Oct 2008
Posts: 31
Helped: 2

05 Nov 2009 13:57 Re: Relation b/w Timing parameter(Tcq) & PVT(Process,Vol

I guess what u'r seeing is "Temperature Inversion" Concept

for your 4 cases
c1) Fast , high Voltage , low Temp ( ffhl)
c2) Fast , high Voltage , high Temp ( ffhh)
c3) slow , low voltage , low Temp ( ssll)
c4) slow , low voltage , high Temp (sslh)

for 65nm and above , and at good voltage levels , Delay follow this trend
c1 < c2 < c3 < c4
Hence people traditionally use sslh ( c4) for Max time runs and
ffhl (c1) for Min time runs.

But in 45nm and below , or at low Voltage levels , Delay is following this
trend
c1 < c2 < c4 < c3
hence people nowadays run their maxtime at both ssll (c3) and sslh (c4)
and pick the worst case.

----------------------------
Here is some info behind "Temperature Inversion" Concept
Current = K . Mobility . ( Vgs - Vt)^b

As temperature increases ,
Mobility decreases ,
hence current decreases,
hence delay increases
(i.e as Temp increases , Mobility tries to increase Delay)

Also as temperature increases,
Vt decreases,
hence current increases,
hence delay decreases
(i.e as Temp increases , threshold Vt tries to decrease Delay)

In Old generations 65nm above , Mobility used to dominate delay term.
But in New generations 40nm & below , even Vt is dominating delay term.

For more info , google "Temperature inversion"
---------------------------------

Hope you understood the concept ( A probable Interview Question for
ASIC Design position!)

vikram789

Joined: 01 Aug 2008
Posts: 36

06 Nov 2009 8:08 Re: Relation b/w Timing parameter(Tcq) & PVT(Process,Vol

thats perfectly fine but why arent temperature inversion effects are seen on the fast ones, as we can see that effects of temperature inversion ,as technology shinks , are seen only on slow ones and not on fast ones

Google
AdSense
Google Adsense

06 Nov 2009 8:08 Ads

koggestone

Joined: 16 Oct 2008
Posts: 31
Helped: 2

06 Nov 2009 17:12 Re: Relation b/w Timing parameter(Tcq) & PVT(Process,Vol

vikram789 wrote:

for Fast transistors, we use "High" Voltage , hence effect of Temperature is
not that important.

"Temperature Inversion" is typically at "Low" Voltages

in your setup , c1 and c2 (Fast cases) are both at High Voltages
c3 and c4 (slow cases) are both at Low voltages.

For fun , may be try these 2 corners
cc1) fast transistors , low voltage , low temperature (ffll)
cc2) fast transistors , low voltage , high temperature (fflh)
u might see temperature inversion effect at these fast transistors.
i.e cc2 < cc1 ( i.e delay of cc2 is less than cc1)
But in Real life , nobody cares about these 2 corners as they are not
extreme cases

vikram789

Joined: 01 Aug 2008
Posts: 36

09 Nov 2009 6:23 Re: Relation b/w Timing parameter(Tcq) & PVT(Process,Vol

okay thats fine , i observed the same but this explains the trend of tcq for mos with low voltage taking in effect of temperature inversion, but how are we going to justify the trend for mos running on high voltage
e.g
ffqb0p99vn40c | ffqb0p99v125c
0.397 |0.464

i.e what justification we have for saying that Tcq INCREASES as Temp INCREASES for high voltage mos. CONSIDER UR STATEMENT WHERE U SAID for 40nm or below Vt dominates mobility and hence Tcq should decrease as temp increase

koggestone

Joined: 16 Oct 2008
Posts: 31
Helped: 2

09 Nov 2009 16:21 Re: Relation b/w Timing parameter(Tcq) & PVT(Process,Vol

vikram789 wrote:

The equation of current looks like
Current = K . Mobility . ( Vgs - Vt)^b
where Mobility and Vt are function of Temperature ( they decrease with increase
in temperature.

If u draw current vs Temp Plot at High Vdd , u will see a monotonically
decreasing curve , whereas same plot at Low Vdd , u will see a U shape curve.

In simple layman terms , the reasoning behind Vdd -Vt dominates at Low
voltages is , suppose u earn 1 Dollar (Vdd) and u spent 10 cents (Vt) ,
that's not a big effect . But if u earn 60 cents but u spent 10 cents (Vt) ,
then u will start feeling concerned.

As we move to scale lower process geometries (40nm ) , Vt is not scaling
proportionately (bcoz of leakage concerns) . But since people are decreasing
Vdd than the process recommended nominal , to save Power , we are
seeing that Vgs-Vt term also important in addition to Mobility.

For more info on those U shape curves , refer to some conference or
Journal (JSSC) papers in IEEE xplore .

vikram789

Joined: 01 Aug 2008
Posts: 36

10 Nov 2009 5:05 Re: Relation b/w Timing parameter(Tcq) & PVT(Process,Vol

hi , i have observed U shape curve at low voltages, as u r saying,
ffqb0p99vn40c 5.347695574325e-10
ffqb0p99v0c 5.409813293164e-10 ....bump
ffqb0p99v125c 5.207684650105e-10

but in some cases even at low voltages i havent observed U shape transition
ssqb0p72vn40c 2.427
ssqb0p72v0c 2.254
ssqb0p72v125c 1.883 ....decreasing monotonically

well these are secondary things what i would liike to learn is the reason behind the nature of these transitions, though we have discused the reason behind the transition at low voltages we havent covered the reason for transition at high voltages, if u can do me a favour plz give a link to IEEE papers that u were taking about ...

Thankyou