Vds-Vdsat to keep a transistor in saturation

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PSG

Joined: 04 Feb 2009
Posts: 13

04 Nov 2009 23:40 Vds-Vdsat to keep a transistor in saturation

Hi,

This probably sounds like a dumb question, but if I want to keep my MOS in saturation, I know I need to keep the Vds large enough, and instinctively it would make sense to keep it above Vdsat ... if I missed something already, stop me right there!
So now the question is how much margin do I allow myself: is Vds-Vdsat>0 enough or do I need to have Vds-Vdsat>100mV to play safe. At the other end, in situations where I run out of headroom, can I go with Vds slightly below Vdsat, and if so what is the trade-off.

Thanks in advance for your advice.

PSG

Joined: 04 Feb 2009
Posts: 13

05 Nov 2009 16:03 Vds-Vdsat to keep a transistor in saturation

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snafflekid

Joined: 09 May 2007
Posts: 118
Helped: 16
Location: USA

06 Nov 2009 7:07 Vds-Vdsat to keep a transistor in saturation

Vds>Vgs-Vt is the definition of saturation. In short channel mosfets this is not exact but good enough. If your working circuit depends on 100mV difference on the drain, you must run many test case simulations.

Last edited by snafflekid on 06 Nov 2009 22:42; edited 2 times in total

ravirajdv

Joined: 07 Jan 2007
Posts: 33
Helped: 9
Location: India

06 Nov 2009 15:39 Re: Vds-Vdsat to keep a transistor in saturation

Hi,
Vds-Vdsat=0 is on the verge of saturation (pinch off point). It is better to keep a margin of 100mV - 200mV so that you take care of the effects that exist because of process. supply and temperature variations.
Higher the margin lesser are the effects of the noise, specifically the thermal.

Regards,
RDV

DenisMark

Joined: 16 Sep 2005
Posts: 324
Helped: 66
Location: Russia

17 Nov 2009 6:55 Vds-Vdsat to keep a transistor in saturation

Hi PSG,

Vds-Vdsat>0 is ok (if you keep it for all process corners as well as for bias conditions and temperatures).
Indeed in model Vdsat is actually overestimated. It's higher than point below which Rds starts to reduce.
You can find it out e.g. in:
Tradeoffs and Optimization in Analog CMOS Design by David Binkley