How to design 1 to 8 multiplier

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kunal1514

Joined: 13 Dec 2006
Posts: 90

04 Nov 2009 10:03 How to design 1 to 8 multiplier

Hi all,

How to design 1 to 8 multiplier

ebuddy

Joined: 15 May 2007
Posts: 28
Helped: 1

05 Nov 2009 2:03 Re: How to design 1 to 8 multiplier

Manually, you can either write the boolean table and design the logic, or you can design 1 to 2 mux and cascade them together. Of course, an HDL approach is most effecient.

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cherin

Joined: 18 May 2008
Posts: 8

05 Nov 2009 19:09 Re: How to design 1 to 8 multiplier

module mux_8to1(sel,out,inp1,inp2,inp3,inp4,inp5,inp6,inp7,inp8);

input [2:0] sel;
input inp1,inp2,inp3,inp4,inp5,inp6,inp7,inp8;
output out;

assign out=(sel[2]?(sel[1]?(sel[0]?inp8:inp7):(sel[0]?inp6:inp5)):(sel[1]?(sel[0]?inp4:inp3):(sel[0]?inp2:inp1)));

endmodule

this is the verilog module for an 8 is to 1 mux
As already mentioned, an alternative is to use 7 2:1 muxes in a binary tree structure to make up an 8 is to 1 mux.
Hope this is useful, Cheers!