chichan
Joined: 04 Apr 2007
Posts: 5
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 01 Nov 2009 19:12 Need Help with Sinle-Slope ADC |
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I need to implement a 7-bit single-slope ADC whose structure is shown in the attached file. The counter in the ADC must operate below 10Meg Hz.
However, the voltage output of my integrator cannot vary linearly with time. It looks straight within 1us, but then after 1us it looks like an arc. If the integrator output of my ADC doesn't vary linearly with time, then my ADC fails. What should I do to make the integrator output have a linear relationship with time? Or is there anything I can do to make my ADC meet the specifications?
Could anyone please help me? Your help is deeply appreciated. Thank you very much.
Below is my code for the integrator written in Hspice.
***Current Mirror***
Rs vdd q2s 25k
MQ2 q0g q2g q2s q2s pch W= 3.6um L= 1um
MQ3 q2g q2g vdd vdd pch W= 3um L= 1um
MQ0 q2g q0g gnd gnd nch W= 1um L= 1um
MQ1 q0g q0g gnd gnd nch W= 1um L= 1um
*** Closed loop ***
*** First stage ***
M1 o1 vin cm cm pch W= 6um L= 1um, M=4
M2 o2 vip cm cm pch W= 6um L= 1um, M=4
M3 o1 o1 gnd gnd nch W= 2um L= 4um
M4 o2 o2 gnd gnd nch W= 2um L= 4um
M10 cm q2g vdd vdd pch W= 3um L= 1um, M=4
*** Second stage ***
M7 m7d m7d vdd vdd pch W= 1um L= 5um
M8 out m7d vdd vdd pch W= 1um L= 5um
M5 m7d o1 gnd gnd nch W= 2um L= 4um
M6 out o2 gnd gnd nch W= 2um L= 4um
Cout out gnd 1p
*************************************************************
$Vip vip gnd $dc = 0V
C vin out 8p
R ref vin 150k
Mn1 vin clock out gnd nch W= 2um L= 1um ***NMOS for reset
Vref ref gnd 0V $ac =1V
****** SOURCE ******
vdd vdd gnd dc=3.3v
$Vin vin gnd dc= 1.65V AC =0.5V, 180
Vip vip gnd dc= 1.65V $AC =0.5V, 0 $
*** Reset ***
Vclock clock gnd pulse(0 3.3V 1us 0.05ns 0.05ns 1us 150us)
.TRAN 1n 10U
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