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chibijia
Joined: 16 Jan 2008
Posts: 36
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 01 Nov 2009 16:07 something about synthesis |
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recently,i am learning some eda practical class,involves some software,such as design compile,i use it to synthesis my codes,take div_3freq as example!because it involves multi-clock,when meeted this question,how to handle it!
help;help;help;
and i could not view my frequency_divider wave!
what problem i have!
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01 Nov 2009 16:07 Ads |
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niravbhatt
Joined: 16 Mar 2009
Posts: 30
Helped: 2
Location: Ahmedabad,India
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02 Nov 2009 5:51 Re: something about synthesis |
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As your design consists of more than one clock, your design also consists of clock domain crossing signals.
Please confirm that you have properly used synchronizers and for the CDC signals and followed all CDC rules.
You check this first and then let me know.
--
Regards,
Nirav Bhatt
Added after 4 minutes:
If you don't have any IDEA about CDC, please download below given pdf and get familiar about CDC.
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chibijia
Joined: 16 Jan 2008
Posts: 36
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03 Nov 2009 2:14 something about synthesis |
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| thanks the upstairs!
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