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Phase Locked Loop - transistor sizing forphasedetector
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mytreyi



Joined: 24 Jul 2009
Posts: 6
Location: india
Post01 Nov 2009 14:38   

Phase Locked Loop
please anybody tell me... Is it required transistor sizing when phase detector designing...iam not getting output at the PFD(iam using 0.18um cadence)...
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jesseyu1984918



Joined: 16 Jun 2008
Posts: 13
Helped: 1
Location: Singapore
Post02 Nov 2009 9:49   

Phase Locked Loop
Did you apply too fast input to your logic gate? Usually for D-flip flop, you need enough set-up and hold time in order to make it latch the input, I think you could check on this.
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mytreyi



Joined: 24 Jul 2009
Posts: 6
Location: india
Post02 Nov 2009 13:26   

Phase Locked Loop - transistor sizing forphasedetector
very very thanq.....
i applied delay =0ns
rise time=100ps
fall time=100ps
v1=0v
v2=1.8v
pulse width=20ns
pulse period=40ns
(W/L)n=(W/L)p=240nm/180nm
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dick_freebird



Joined: 04 Mar 2008
Posts: 312
Helped: 45
Location: USA
Post02 Nov 2009 16:24   

Phase Locked Loop - transistor sizing forphasedetector
Try "sliding" the phases past each other looking for the
output to change behavior. At some phase offsets you
-should- see nothing happen. But you need to verify both
"early" and "late" operation.
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mytreyi



Joined: 24 Jul 2009
Posts: 6
Location: india
Post06 Nov 2009 5:33   

Re: Phase Locked Loop - transistor sizing forphasedetector
transistor sizing...is it effected to the output....
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