what is "new" instruction in vhdl ?

EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> what is "new" instruction in vhdl ?

Author

Message

omidsht

Joined: 24 Dec 2007
Posts: 34

31 Oct 2009 6:48 what is "new" instruction in vhdl ?

Hi , what does "new" do in vhdl ?
i see it was used in declaring packages !

Google
AdSense
Google Adsense

31 Oct 2009 6:48 Ads

pini_1

Joined: 18 Jun 2007
Posts: 288
Helped: 17

31 Oct 2009 9:07 Re: what is "new" instruction in vhdl ?

Creates a new item. Take a look on this example which part of a memory I worte:
"....I decided to use a sparse memory model to reduce memory consumption. The idea is that a memory of large address (18 bits) of 16 bits data word consumes, only that much that is written, to the memory model, during simulation...."

http://bknpk.no-ip.biz/my_web/IP_STACK/sram_sparse_vhdl.html

The memory is part of a :"This project implements the lower layers of a standard TCP/IP stack based on a free code from University of Queensland..."