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ramya19
Joined: 29 Oct 2009
Posts: 3
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 29 Oct 2009 13:26 opamp design |
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| I am trying to design an opamp. I have supplied a bias current of 10uA Vsupply=3.3v. 10uA is flowing through the diffpair branches (current mirror as well as input pair) The problem is the input pair transistors are in cutoff and all others are in saturation. Please suggest me what to do.
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standup
Joined: 25 Oct 2006
Posts: 32
Helped: 2
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29 Oct 2009 17:58 opamp design |
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| please check your common input voltage
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29 Oct 2009 17:58 Ads |
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ken_cn
Joined: 09 Oct 2005
Posts: 40
Helped: 2
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03 Nov 2009 15:10 opamp design |
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| I tihink your input common voltage is too low(or high) to turn on the input pair.
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pianomania
Joined: 15 Jun 2006
Posts: 55
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04 Nov 2009 13:32 Re: opamp design - bias current of 10uA Vsupply=3.3v. |
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As others opinion , you should check you commond input range ,
, as my experience ,
the maximum input range is Vdd-Vgs_in-Vds(tail current MOS)
and the minimun is Vss+Vgs+ Vds-Vgs_in , it might be close to Vss , if we use PMOS input . If we use NMOS input , the relationship will be exchanged.
Then by changing the W/L , you can make input operate under saturation.
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