Verilog: LCD initialization

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laserbeak43

Joined: 15 Aug 2008
Posts: 24
Location: Maryland, USA

28 Oct 2009 18:55 Verilog: LCD initialization

hello,
I'm trying to control the LCD on my Spartan3E starter kit without the use of picoblaze. I've written some code to initialize according to the HD44780U Datasheet's init sequence on page 46(4-bits) but I'm not getting anything. At the end of this sequence, I'm trying to get a blinking cursor. The code synthesizes fine, but does nothing on my board.

I was wondering if anyone here can help?

the code is attached, i think it'd be too long to post here. Just in case you're wondering, SF_CEO is held high to disable the board's strataflash and rst is a switch on my board. I've included a .ucf file if you are interested in looking at the constraints.

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laserbeak43

Joined: 15 Aug 2008
Posts: 24
Location: Maryland, USA

29 Oct 2009 4:56 Re: Verilog: LCD initialization

with a friend's help, i've managed to write a new, cleaner looking version of the code. I've attached it to this message. It synthesizes but i get these warnigns:

Quote:

WARNING:Par:288 - The signal clki_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal rst_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:283 - There are 2 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:PhysDesignRules:367 - The signal <clki_IBUF> is incomplete. The signal
WARNING:PhysDesignRules:367 - The signal <rst_IBUF> is incomplete. The signal

of course, the xilinx database is no help with these warnings.

does anyone have any idea what they are?

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dcreddy1980

Joined: 03 Dec 2004
Posts: 189
Helped: 25
Location: Munich, Germany

31 Oct 2009 4:15 Verilog: LCD initialization

The warning you see are not w.r.t code, You haven't defined properly your constraints while synthesis of your design. Please double check if you have constraints on clock and reset pins

laserbeak43

Joined: 15 Aug 2008
Posts: 24
Location: Maryland, USA

31 Oct 2009 16:10 Re: Verilog: LCD initialization

hello,
Thanks for the reply. "w.r.t." code? I'm not sure what that is, but i've taken your advice and compared my constraints file with my user guide list.
I must tell you that I messed around with the file a bit last night and got rid of the warnings once i fiddled with a few things, for example, I've made the rst a button instead of a switch, and also put an LED to indicate that it has been reset. Maybe i should also light an LED to represent a stage of the state sequence as well. hold on....hmmm well the constraints seem to be working still but the states aren't moving according to the LEDs
I was told that i had to make the parameters that i'm using 44-bits to match the clock. I'm not sure if values are 0 based to same way vectors are so i switched between

Code:

parameter myparam = 43'hxx

and

Code:

parameter myparam = 44'hxx

I've noticed no change though. Any suggestions?(New code posted)

Thanks,
Malik

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FvM

Joined: 22 Jan 2008
Posts: 5154
Helped: 766
Location: Bochum, Germany

31 Oct 2009 18:34 Re: Verilog: LCD initialization

Quote:

I was told that i had to make the parameters that i'm using 44-bits to match the clock.

The guy, who suggested this seems to have serious problems with calculating larger numbers...

As a first point, the clock is 50 MHz, not 50 GHz. So halfseconds is 25000000. You actually need 25 bits rather than 44 bits to represent it.

Code:

parameter halfSec = 25'd25000000;

Even the 500 second value that you specified, won't need more than 35 bits, by the way. But you probably give up your test, before it elapsed...

As a next point, state has a too small width, so the state machine can't work at all. Curiously you have 6 bit wide constants (0x2A the highest), an inappropriate 5'h2A notation (should be 6'h2A accordingly) and a 4 bit wide register reg [3:0].

Obviously value range, constant notation and register wide must fit. Correct these points and try again.

laserbeak43

Joined: 15 Aug 2008
Posts: 24
Location: Maryland, USA

31 Oct 2009 19:19 Re: Verilog: LCD initialization

FvM wrote:

Quote:

I was told that i had to make the parameters that i'm using 44-bits to match the clock.

The guy, who suggested this seems to have serious problems with calculating larger numbers...

Heh, how embarrassing. In my friend's defense he just saw the bit-width i had created for my count reg and suggested that i make the bit-widths match so that the concatenation works correctly in the state machines. If he hadn't been getting off from what was probably a long day of work, i'm sure he would've noticed the issue. I, on the other hand, should have taken that bit-width into consideration when I had first started this revamp project

FvM wrote:

As a next point, state has a too small width, so the state machine can't work at all. Curiously you have 6 bit wide constants (0x2A the highest), an inappropriate 5'h2A notation (should be 6'h2A accordingly) and a 4 bit wide register reg [3:0].
.

hmm oops. wow can't believe i've missed all of that. I think i've made them match, but again, I'm not sure if values are 0 based or not. i don't think so though
so clock will be

Code:

reg [24:0] cnt;

and

Code:

parameter halfsec = 25'd25000000

thanks for noticing this.
I've tried it and it still isn't working though... I've attached a new version if anyone would be so kind as to look
thanks again
Malik

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FvM

Joined: 22 Jan 2008
Posts: 5154
Helped: 766
Location: Bochum, Germany

31 Oct 2009 19:57 Re: Verilog: LCD initialization

Better, but still incorrect.

Your assigning 6 bits to a seven bit register LEDl[6:0], unfortunately all other fields on the left are shifted by one bit, so the state
machine is still non-operational. That's the price you pay for using this highly elegant concatenation construct for your state machine:
One bit wrong and everything mixed up.

The below parameter is also calculated incorrectly, I don't know why you are using hexadecimal notation instead of readable decimal?
parameter us2 = 25'h100000; //2ms

laserbeak43

Joined: 15 Aug 2008
Posts: 24
Location: Maryland, USA

01 Nov 2009 0:41 Re: Verilog: LCD initialization

FvM wrote:

hmmm us2 should have been

Code:

ms2 = 25'd100000

heh, what a mess. Also, i've fixed the bit widths of the 6-bit register values.
still nothing of course. yeah the way i originally did it is what i'm more used to. I just thought it might be better to learn how to do it in a cleaner style. Either way, I'm not very good at catching my mistakes yet, and ISE certainly isnt going to give me any warnings....

Updated code is attached..

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laserbeak43

Joined: 15 Aug 2008
Posts: 24
Location: Maryland, USA

02 Nov 2009 3:54 Re: Verilog: LCD initialization

My latest version of the code explains why the state isn't working, it says it's a constant 0 value. I just can't figure why it's doing that...

Quote:

=========================================================================
* HDL Synthesis *
=========================================================================

Performing bidirectional port resolution...
INFO:Xst:2679 - Register <state> in unit <LCDInit> has a constant value of 000000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <LEDl<6>> in unit <LCDInit> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <LEDl<5>> in unit <LCDInit> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <LEDl<4>> in unit <LCDInit> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <LEDl<3>> in unit <LCDInit> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <WE> in unit <LCDInit> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <RS> in unit <LCDInit> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <RDB> in unit <LCDInit> has a constant value of 0000 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <LEDl<2>> in unit <LCDInit> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <LEDl<1>> in unit <LCDInit> has a constant value of 0 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <LEDl<0>> in unit <LCDInit> has a constant value of 1 during circuit operation. The register is replaced by logic.
INFO:Xst:2679 - Register <CE> in unit <LCDInit> has a constant value of 0 during circuit operation. The register is replaced by logic.

Synthesizing Unit <LCDInit>.
Related source file is "init.v".
Found 4-bit tristate buffer for signal <dbo>.
Found 25-bit down counter for signal <cnt>.
Found 1-bit register for signal <LEDl<7>>.
Summary:
inferred 1 Counter(s).
inferred 1 D-type flip-flop(s).
inferred 4 Tristate(s).
Unit <LCDInit> synthesized.

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dcreddy1980

Joined: 03 Dec 2004
Posts: 189
Helped: 25
Location: Munich, Germany

02 Nov 2009 6:23 Re: Verilog: LCD initialization

Code:

First thing..."LEDl[7] <= rst;" is a bad coding style

Your code looks like this :

if(rst) begin {cnt, state} <= 0; LEDl[7] <= rst; end
else
if(|cnt) cnt <= cnt - 1;
else
begin

u r case statement logic

end

I really didnt understand why u have this logic "if(|cnt) cnt <= cnt - 1;"

I think u might have seen transition from state 6'h0 to 6'h1 and you would in that state for ever. You will now have cnt = halfSec which will have some defined value and this statement will always becomes true "if(|cnt) cnt <= cnt - 1;" because u have atealst one-bit active in that cnt signal, it will take a long to go down to zero. Once it becomes zero, u will see another state transition.

Is this waht u want or Did i miss any point??

laserbeak43

Joined: 15 Aug 2008
Posts: 24
Location: Maryland, USA

02 Nov 2009 7:12 Re: Verilog: LCD initialization

my new code cycles through all of the states but it does nothing to my LCD.

Quote:

I really didnt understand why u have this logic "if(|cnt) cnt <= cnt - 1;"
...
Is this waht u want or Did i miss any point??

if I understand you correctly you're asking why i'm taking half of a second to cycle through the states? for ease of writting. I was told that it will still work even if it is slow, and i can fix it later, once i can get the lcd initialized. but i still haven't gotten it working.

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FvM

Joined: 22 Jan 2008
Posts: 5154
Helped: 766
Location: Bochum, Germany

02 Nov 2009 9:11 Re: Verilog: LCD initialization

Quote:

Better, but still incorrect.

You're operating the state machine now, but don't generate meaningful output because of the below line. It's tristate most of the time. As long as you don't attempt to read from the display, you can simply enable the data line permanently.

Code:

assign dbo = (state==4'hA)? RDB : 4'bZZZZ;

Finally, you should care, if you're performing a valid initialization sequence. I wasn't motivated to decode the sequence, I just saw, that it's not the recommended "Initializing by Instruction" 4-Bit sequence, that can be expected to work independant of a previous display hardware reset.

By the way, don't you have a simulator or hardware debugger tool with your Xilinx enviroment to trace the design operation yourself?

laserbeak43

Joined: 15 Aug 2008
Posts: 24
Location: Maryland, USA

02 Nov 2009 15:21 Re: Verilog: LCD initialization

ok so for now i'll just use

Code:

assign dbo = RDB;

It's clearing now, but no cursor comes up, i think i need to add the cursor code now.

Quote:

well the LCD is compatible with an Hitachi HD44780U, as you could've guessed
but it's a Sitronix ST7066U page 25 of this document shows the 4-bit init sequence. Should i just use the Hitachi version?

Quote:

By the way, don't you have a simulator or hardware debugger tool with your Xilinx enviroment to trace the design operation yourself?

Well ISE has a simulator, but i don't know how to write testbenches. I guess it's something I should learn how to do, but to be honest, it's quite intimidating, since the code for a testbench is usually 4x longer than the actual design... I'm looking for an alternative, like hardware debugging or something.[/code]

FvM

Joined: 22 Jan 2008
Posts: 5154
Helped: 766
Location: Bochum, Germany

03 Nov 2009 9:15 Re: Verilog: LCD initialization

Quote:

since the code for a testbench is usually 4x longer than the actual design

In this case, it's not more than supplying a clock and reset signal, maximum 10 lines of code, plus the instantiation of the DUT as a module.

Quote:

Should i just use the Hitachi version?

No, if you have reason to assume, that the present one is correct as well. As I said, the difference can be in requiring a previous hardware reset. This condition can be expected after power on, but e.g. not after reloading a design. Performing the classical Hitachi fail-safe reset sequence possibly can avoid problems in testing.

As another remark, as a next step, you may want to design a state machine, that can execute complete 8-Bit writes without needing to cut them in individual steps.

laserbeak43

Joined: 15 Aug 2008
Posts: 24
Location: Maryland, USA

03 Nov 2009 15:07 Re: Verilog: LCD initialization

FvM wrote:

Quote:

since the code for a testbench is usually 4x longer than the actual design

In this case, it's not more than supplying a clock and reset signal, maximum 10 lines of code, plus the instantiation of the DUT as a module.

SOUNDS easy enough Smile

FvM wrote:

Quote:

Should i just use the Hitachi version?

Not sure i'm familiar with this method, if it's in the Hitachi data-sheet, I've seen it though. I'm thinking a counter that starts when the system powers on and counts for like 50?s to let the LCD reach full power then init there.

FvM wrote:

As another remark, as a next step, you may want to design a state machine, that can execute complete 8-Bit writes without needing to cut them in individual steps.

well my board communicates with 4 bits but yeah an 8bit version would've been nice Smile