vhdl: three branch process question

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pini_1

Joined: 18 Jun 2007
Posts: 288
Helped: 17

28 Oct 2009 13:37 vhdl: three branch process question

I wrote behavioral model for a SRAM device. The model is based on sparse memory, which I found on doulos site. I changed the read drive and write store logic to fit my asynchronous memory.
When I simulated with GHDL, I encounter a problem. Sometimes GHDL would not drive the read data bus, even though that a print message one line before drive verifies that it should.
With a little change to the code style, GHDL works okay. The change is merely:
canceling the positive edge detection to regular logic.
Please comment on this issue. Is it a VHDL typo or a GHDL bug.

The problemtic code follows and the entire code is at:
http://bknpk.no-ip.biz/my_web/IP_STACK/sram_sparse_vhdl.html

process (lcen, loen, lwen, laddr)
…
begin
if(lcen = '0' and lwen = '1' and loen ='0') then --read
Get(laddr, D);
ldata <= D;--sometimes does not work ??
end if;

--stop driving the data
if loen'EVENT and loen = '1' then
ldata <= (others => 'Z');
end if;

--The next line offended GHDL please comment .
--if lwen'EVENT and lwen = '1' then
if lwen = '0' then
if(lcen = '0') then --write

Set (laddr, ldata);
end if;
end if;

avimit

Joined: 16 Nov 2005
Posts: 417
Helped: 69
Location: Fleet, UK

28 Oct 2009 14:35 Re: vhdl: three branch process question

Try one thing.
Instead of using
if loen'EVENT and loen = '1' then
use
if(rising_edge(loen)) then

and let me know
Avi
http://www.vlsiip.com

pini_1

Joined: 18 Jun 2007
Posts: 288
Helped: 17

28 Oct 2009 15:42 Re: vhdl: three branch process question

No it did solve the issue. In my opinion GHDL implements both in the same way.

FvM

Joined: 22 Jan 2008
Posts: 5161
Helped: 767
Location: Bochum, Germany

28 Oct 2009 16:13 Re: vhdl: three branch process question

Quote:

In my opinion GHDL implements both in the same way.

No surprize, because the two expressions are exactly synonymous.

There is a rather confusing mix of edge sensitive and level sensitive statements. I doubt, if this can be a suitable behavioral description of the device. It's completely unsynthesizable anyway. In my opinion, a SRAM won't need edge sensitive conditions, possibly except for the write to storage cells action. The control of
data buffer enables must be surely level sensitive.

pini_1

Joined: 18 Jun 2007
Posts: 288
Helped: 17

28 Oct 2009 16:18 Re: vhdl: three branch process question

I said that the RAM is behavioral model for simulation, so synthesis is not an issue.

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aliputa

Joined: 01 Nov 2009
Posts: 3
Location: China

01 Nov 2009 17:00 Re: vhdl: three branch process question

hello, i think you maybe should check the SRAM's code clearly, 1. it's a synchronous SRAM or an asynchronous SRAM? 2. your code(writed by yourself) is a synchronous or an asynchronous?
and some type of SRAM need a pulse wave for WRITE(or READ) in every operation period.
i think the code which writed by yourself should adapt the SRAM's code, maybe there is something not so match between two codes.

it's just my opinion