Instantiating a verilog model in VHDL, how to deal with para

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kel8157

Joined: 14 Nov 2007
Posts: 84
Helped: 2

27 Oct 2009 9:18 Instantiating a verilog model in VHDL, how to deal with para

meters?

Let's say I wish to instantiate a RAM verilog model, which uses a init file in the parameter..

How do I change this filename in my VHDL file?

I use ncsim 8+..

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