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Riffi
Joined: 26 Oct 2009
Posts: 3
Location: PARIS
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 26 Oct 2009 21:07 DFT explanation |
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Hi every body,
I’m new one in DFT, I would like someone to clarify me those points bellow:
What is difference between, Test_mode (TM) pin and Scan_Enable pin?
And at what steep to insert them in RTL or in synthesis phase?
What is drawback to use latch in design I mean it negative effect on Test Coverage and how?
Thank you for your help
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26 Oct 2009 21:07 Ads |
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neetinsingh
Joined: 18 Jun 2007
Posts: 51
Helped: 1
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27 Oct 2009 19:33 Re: DFT explanation |
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What is difference between, Test_mode (TM) pin and Scan_Enable pin?
Test_mode pin is use to put SOC/ASIC into TEST MODE or Functional mode. There are various test modes in DFT like ICTECT, IDDQ, IO BIST , AC/DC TEST, MBIST, JTAG etc. Scan_enable is only significant in the test mode ie when test_mode signal is asserted for the test mode. Scan_en is being used to enable the Scan able Flops to capture the data from the data pin instead scan_in pin. In basic functionality scan_en is held high during the shift mode i.e data will be captured in flop from the scan_in pin and its held low to capture data from the data pin. Kindly refer circuit diagram of a scab flop.
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Riffi
Joined: 26 Oct 2009
Posts: 3
Location: PARIS
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29 Oct 2009 21:50 Re: DFT explanation |
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thank you neetinsingh ,I got it !
Could someone clarify those 2 questions to me!
1-At what steps to specify scan_enable /TM input port in RTL or in synthesis?
2-What is drawback to use latch in design I mean it negative effect on Test Coverage and how?
Excuse my fragile English language
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shelby
Joined: 04 Jan 2007
Posts: 76
Helped: 10
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31 Oct 2009 19:56 DFT explanation |
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If you have scan clocks that need to be muxed in with functional clocks, this needs to be done in RTL. This may be done at SOC level and not needed for block level implementation. You may also need to bypass any internally generated reset signals in RTL for test mode as well.
For scan enable you may need to define logic to generate this signal. Again, this may be at SOC level and not needed for block level. The connection of this signal to the flops are not done until you synthesis your design and do your scan insertion.
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Riffi
Joined: 26 Oct 2009
Posts: 3
Location: PARIS
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08 Nov 2009 18:59 Re: DFT explanation basic nomenclature |
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Thank you shelby!
I'm newer in DFT Domain,
could you please , clarify for me the difference for inserting at SOC (System On Chip) level and Block level ?
Regards
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