synopsys design compiler -- commands to set test cases

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linny_chen

Joined: 19 Aug 2009
Posts: 4
Location: Aachen, Germany

26 Oct 2009 15:32 synopsys design compiler -- commands to set test cases

There is one command in synopsys design compiler called "set_case_analysis", which can set some constant test case on certain ports, without optimized away components influenced by this constant setting. But "set_case_analysis" can only set signal values like 0, 1, rising edge and falling edge to the test ports. Could anyone tell me if there is such similar commands which could set values like Z, -, U, X etc? Thanks a lot!

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ljxpjpjljx

Joined: 05 May 2008
Posts: 534
Helped: 12
Location: Shang Hai

27 Oct 2009 5:18 Re: synopsys design compiler -- commands to set test cases

why you want to do so ?

linny_chen

Joined: 19 Aug 2009
Posts: 4
Location: Aachen, Germany

27 Oct 2009 9:01 synopsys design compiler -- commands to set test cases

Hi, friend,

I have some multiplexers inside my circuit. I would like to set a value on the selection port of multiplexer to guide Design Compiler when it is calculating the critical path. For some multiplexers I want neither of the input to be selected.