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VHDL equivalent for Verilog readmemb ?
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deepa1206



Joined: 12 Jun 2009
Posts: 12
Post25 Oct 2009 19:44   

VHDL equivalent for Verilog readmemb ?
Hi Could anybody let me know what the VHDL equivalent of "$readmemb" (in Verilog) would be?

Thanks
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pini_1



Joined: 18 Jun 2007
Posts: 288
Helped: 17
Post25 Oct 2009 19:58   

Re: VHDL equivalent for Verilog readmemb ?
You need to write by yiurself.
If you need a memory model: a sparse memory model ...take a look at
http://bknpk.no-ip.biz/my_web/IP_STACK/sram_sparse_vhdl.html
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deepa1206



Joined: 12 Jun 2009
Posts: 12
Post25 Oct 2009 21:11   

Re: VHDL equivalent for Verilog readmemb ?
Thank you for your reply. I want to read a .txt file and load its contents in a ROM/RAM. Can I make this procedure synthesizable?

Please let me know.
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Post25 Oct 2009 21:11   

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ljxpjpjljx



Joined: 05 May 2008
Posts: 533
Helped: 12
Location: Shang Hai
Post26 Oct 2009 5:05   

Re: VHDL equivalent for Verilog readmemb ?
I think this process can't be synthesised!
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