electronics forum

Rules | Recent posts | topic RSS | Search | Register  | Log in

Triple well tie-down rule in IBM 65nm cmos10lpe process
Post new topic  Reply to topic    EDAboard.com Forum Index -> Analog Circuit Design -> Triple well tie-down rule in IBM 65nm cmos10lpe process
Author Message
chickenvlsi



Joined: 04 Jun 2009
Posts: 13
Post19 Oct 2009 4:22   

Triple well tie-down rule in IBM 65nm cmos10lpe process
Hi everyone,
We are using IBM 65nm cmos10lpe process.
Our design used a triple-well RF nfet (nfettw_rf). However, when we checked DRC with Calibre, the tool generated the following result:
"Triple well tie-down rule: [(T3 not over NW) touching gate] must touch RX, which is electrically connected to (RX over NW) through M1"

Could you please explain more about this rule and let me know how to fix the violation of this rule?

Thank you very much
Back to top
Google
AdSense
Google Adsense
Post19 Oct 2009 4:22   

Ads


Back to top
oermens



Joined: 19 Nov 2005
Posts: 332
Helped: 37
Location: canada
Post30 Oct 2009 15:58   

Triple well tie-down rule in IBM 65nm cmos10lpe process
You can try asking on MOSIS User Group if you got the PDK throught them:

http://tech.groups.yahoo.com/group/MOSIS_Users_Group/
Back to top
Arabic versionBulgarian versionCatalan versionCzech versionDanish versionGerman versionGreek versionEnglish versionSpanish versionFinnish versionFrench versionHindi versionCroatian versionIndonesian versionItalian versionHebrew versionJapanese versionKorean versionLithuanian versionLatvian versionDutch versionNorwegian versionPolish versionPortuguese versionRomanian versionRussian versionSlovak versionSlovenian versionSerbian versionSwedish versionTagalog versionUkrainian versionVietnamese versionChinese version
Post new topic  Reply to topic    EDAboard.com Forum Index -> Analog Circuit Design -> Triple well tie-down rule in IBM 65nm cmos10lpe process
Page 1 of 1 All times are GMT + 1 Hour
Similar topics:
twin well and triple well CMOS process (9)
DISCUSSION: RF CMOS process - triple-well NMOS (2)
Performance Difference between n-well and dual well process (1)
Why N-well Process but not P-well Prcoess???? (6)
Q:tie source and body together in TSMC013 RF process (1)
what should be concerned when design with 65nm process? (4)
0.18 um twin well process? (1)
Deep n-well process??? (3)
Twin Well CMOS Process (2)
Twin well cmos process (7)


Abuse || Administrator || Moderators || Support us || sitemap
topic RSS