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vlsi_design
Joined: 08 Oct 2009
Posts: 1
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 08 Oct 2009 14:43 Setup & Hold Time |
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Hi,
Can anyone tell me, from where the concept of setup and hold time came?
Defination wise its ok. but I want to understand how these terms are being calculated, other than calculated equations.
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wenty
Joined: 05 Oct 2004
Posts: 18
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10 Oct 2009 6:46 Re: Setup & Hold Time |
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think about this, you have a 5 min walk to a elevator door, you got to start to walk toward the door at least 5 mins ealier than the door begin to close to make sure you can take the elevator, this is the setup time;once you are right at the point of the closing door, you got to continue to walk inside a little bit to let the door close behind you, how far you need to walk further depend on how thick the door is, you do not want to block the door, here comes the hold time. 
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ljxpjpjljx
Joined: 05 May 2008
Posts: 533
Helped: 12
Location: Shang Hai
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10 Oct 2009 7:13 Re: Setup & Hold Time |
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| setup time and hold time deside your design frequency and meta-stability!
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10 Oct 2009 7:13 Ads |
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camr
Joined: 22 Sep 2009
Posts: 2
Location: Western U.S.
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12 Oct 2009 7:09 Setup & Hold Time |
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When you talk about setup and hold, it means there is a clock edge or similar event that triggers the capture of an input's value. The value of the input must remain stable during a specific window around this event defined by the details of the circuit involved, including relative trace lengths, device sizes, switching time, capacitance, etc.
So you must prepare or "set up" the inputs to the right values before a certain time, and you must then "hold" them at that value at least until a certain later time, else you risk unpredictable / undesired behavior.
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niravbhatt
Joined: 16 Mar 2009
Posts: 30
Helped: 2
Location: Ahmedabad,India
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23 Oct 2009 6:37 Re: Setup & Hold Time |
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While designing any hardware, metastability is the key issue when signal is clocked.
So, if you are clocking/registering any signal and that is getting changed during the setup time (fraction of time before clock edge)/ hold time (fraction of time after clock edge), what hardware should consider that signal level either 0 or 1 ? and sometimes the signal may have intermediate logic level. So, this will force metastability in the design and design may or may not work correctly (depends on the Hardware logic). It will be difficult and costly to debug this kind of errors in the design and rectify it.
So, there are few Clock Domain protocols introduced by the designer to make sure that any signal clocked should be enough stable for fraction of time before and after the clock edge. So, there is no confusion for the real hardware what to consider the signal level either o or 1 and design will surely work correctly. It will be easy to debug any problem related to clock domain.
I hope this gives you a brief answer to your question.
If any query, please let me know.
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