what is logical Tie off cells ?where i can use those cells

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vamsi_addagada

Joined: 05 Jul 2007
Posts: 132
Helped: 3
Location: bangalore

24 Sep 2009 6:20 what is logical Tie off cells ?where i can use those cells

what is logical Tie off cells and Tie on cell?where i can use those cells

kel8157

Joined: 14 Nov 2007
Posts: 84
Helped: 2

03 Nov 2009 8:44 what is logical Tie off cells ?where i can use those cells

Yes.. I also want to know. I found some designs use 1'b0 or generated logic_0 (using a DFF) in the same module, but don't undersrtnad what's the difference.

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ebuddy

Joined: 15 May 2007
Posts: 28
Helped: 1

05 Nov 2009 2:07 Re: what is logical Tie off cells ?where i can use those ce

The constant 1'b0 or 1'b1 in HDL is realized with a wire connecting to VDD or GND. That is fine until you consider the ESD issue where a gate of a MOS FET is connecting directly to the power supply or ground. That's where the tie on/off gates come in. They are usually provided by the standard cell library and synthesis tool can pick them up automatically.