Rules | Recent posts | topic RSS | Search | Register  | Log in

Formal Verification of Mentor

 
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital)
Author Message
ljkong



Joined: 18 Jul 2002
Posts: 128
Helped: 1
Location: P.R.C
Post22 Jan 2003 3:46   Formal Verification of Mentor
Whole-Design Formal Verification of a
5-Million Gate Design by Equivalence
Checking Is Possible with a Small
Memory Footprint

Sorry, but you need login in to view this attachment
Back to top
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital)
Page 1 of 1 All times are GMT + 1 Hour


Abuse
Administrator
Moderators
topic RSS 
sitemap