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fly_fish
Joined: 06 Jul 2004
Posts: 33
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 28 Aug 2009 13:23 simalated |
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I have designed a dual-band VCO in charted RF 0.18um CMOS 1P6M process.The VCO's measured frequency is lower than the simalated freauency. The differency is 100MHz. This results my PLL circuit can't lock. ps: The VCO 's mid-frequency is 1.2G/1.5G. Also, I have extracted R-C parameter from the VCO layout.
Anyone knows the reason?
Another question: how to design a test circuit to verify the new IC process's parameter?
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dick_freebird
Joined: 04 Mar 2008
Posts: 312
Helped: 45
Location: USA
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31 Aug 2009 2:00 Re: VCO's measured frequency is far away from it's simalated |
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At that frequency I would not find it surprising to be 6-8% off from simulated
(your process controls on many key components, are worse than that, let alone
the accuracy with which you may have (or not) modeled the parasitic loadings,
supply droop, wirebond effects and so on.
I have found trouble more than once, trying to test oscillation frequency at
probe. Supply can get mighty busy if you didn't build in enough on-chip
decoupling to kill internal switching spikes (Qswitching should be less than
10% of Qdecouple is my rule of thumb).
You will want to approach the problem with an orderly list of the possible
shortfalls, and knock them down one by one (preferably in simulation, by
adding realism for each until you see something start to make sense).
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fly_fish
Joined: 06 Jul 2004
Posts: 33
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03 Sep 2009 1:03 Re: VCO's measured frequency is far away from it's simalated |
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Thank you,dick_freebird! You give me very useful advice.
"Qswitching should be less than 10% of Qdecouple". I can't understand it.
I think suply drop and wirebond effects are not the reason because suply drop will cause VCO's oscillaate frequency arise and VCO's outputs are directly sent to Mixer and Divider,there are no wirebond.
Maybe the parasitic loadings are key reasons. I will simulate its effect.
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