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Gate level netlist checks before taking to P and R
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> Gate level netlist checks before taking to P and R
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arjun1110



Joined: 03 Jul 2008
Posts: 76
Helped: 2
Location: Bangalore,India
Post02 Aug 2009 2:18   

why nets are ideal in gate level netlist
Hi,

Can someone tell me what all the checks need to perform on synthisised gate level netlist before taking in P and R other than LEC.

For example: Multi driven nets, assign statements

These are the two things I know any other things we need to look into the netlist.

If you know please share with us.

Thanks in advance.

Regards,
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Post02 Aug 2009 2:18   

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pini_1



Joined: 18 Jun 2007
Posts: 290
Helped: 17
Post02 Aug 2009 7:38   

basic netlist checks
To verify that the synthesis process end okay. If something fails at the end of P and R, it would be easier to debug.

Take a look at
http://bknpk.no-ip.biz/my_web/ComplexMultiplier/Syn_5.html

Digital Design
Synthesis General Flow

1. Post synthesis simulation is strongly recommended.
....
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D Saurabh



Joined: 03 Jun 2009
Posts: 8
Helped: 1
Location: Singapore
Post04 Aug 2009 3:17   

gate level netlist site:www.edaboard.com
Also check for floating nets. Best thing would be to go through all the Errors and Warnings in the synthesis log file and fix all of them. The fewer the unfixed warnings, the more robust is the netlist you pass on to backend.

-D
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arjun1110



Joined: 03 Jul 2008
Posts: 76
Helped: 2
Location: Bangalore,India
Post04 Aug 2009 3:36   

Re: Gate level netlist checks before taking to P and R
Thanks Saurabh,

I have one more question on skew, do you know the significance of global skew and which command is used to set global skew?

If you know Please share you answer with us.

Regards,
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Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> Gate level netlist checks before taking to P and R
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