How to simulate SPI interface in ADE?

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walker5678

Joined: 17 May 2006
Posts: 178
Helped: 4

28 Jul 2009 12:34 vpwl format

I am simulating a circuit with SPI interface in analog design environment.
There need DIN and DCLK singal input. I am using vpwl and vpulse to generate these signal, however if I want to simulate different clock frequency, i must remodify every parameters of the vpwl and vpulse source, which is very boring.
Anybody knows how to simulate such digital interface in ADE , or , is there any other better tools to simulate it?
Thanks a lot.

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erikl

Joined: 09 Sep 2008
Posts: 737
Helped: 139
Location: Germany

28 Jul 2009 12:48 vpwl variable

walker5678 wrote:

... if I want to simulate different clock frequency, i must remodify every parameters of the vpwl and vpulse source, which is very boring.

Shouldn't it be possible to relate all parameters to a single parameter (clock frequency), then sweep this one?

walker5678

Joined: 17 May 2006
Posts: 178
Helped: 4

29 Jul 2009 1:20 vpwl support design variable

yes, i am also thinking that, but how to write the PWL file? What is the format of PWL file?
If I set a variable called frequency in the PWL file, i can use vpwlf source to generate the singal.

JoannesPaulus

Joined: 19 Mar 2008
Posts: 261
Helped: 44
Location: USA

29 Jul 2009 1:40 vpwlf variable

use the vpulse instead of the vpwlf and put your parameters in the delay, rise time, fall time pulse width and period boxes. For instance you can define:
dclk_freq=1e6, dclk_tp=1/dclk_freq, dclk_tr=1e-9, dclk_tf=1e-9, and dclk_tw=0.5*dclk_tp-dclk_tr.
Then you only need to change dclk_freq and your new clock is ready!

walker5678

Joined: 17 May 2006
Posts: 178
Helped: 4

29 Jul 2009 4:45 ade vpwlf format

However, for DCLK, between every 8 clocks there is a blanking time, which is also need to be adjust.

and DIN is not a pulse , but a constant logical level during one whole clock cycle.

Added after 1 hours 13 minutes:

anybody has an example pwl file , please kindly share. Thanks !

erikl

Joined: 09 Sep 2008
Posts: 737
Helped: 139
Location: Germany

29 Jul 2009 11:05 spi interface design

walker5678 wrote:

What is the format of PWL file?

walker5678 wrote:

anybody has an example pwl file , please kindly share. Thanks !

The format is: <time> <white space> <voltage>
i.e.:
<time0> <voltage0>
<time1> <voltage1>
............. ................

... however - at least in my setUp - variables in the vpwlf file are not supported. I used OS tools (Unix, Linux) to calculate the real values from the parameters.
Good luck! erikl

pit1000

Joined: 26 Jan 2005
Posts: 137
Helped: 32

29 Jul 2009 12:40 spi profile clock

If you use MMSIM 6.0 or higher version it is possible to set digital signals by means of digital vector file otherwise better to use ULTRASIM.

JoannesPaulus

Joined: 19 Mar 2008
Posts: 261
Helped: 44
Location: USA

29 Jul 2009 16:52 vpwl parameters

For the blanking time, you could use a second signal source and do a logical AND with DCLK.

walker5678

Joined: 17 May 2006
Posts: 178
Helped: 4

30 Jul 2009 4:32 How to simulate SPI interface in ADE?

hi, erikl:
thanks, it works.

erikl

Joined: 09 Sep 2008
Posts: 737
Helped: 139
Location: Germany

30 Jul 2009 9:12 Re: How to simulate SPI interface in ADE?

walker5678 wrote:

hi, erikl:
thanks, it works.
BTW, you can use evalstring(desVar(\"vdd\")) to let pwl file support design variable. vdd is an example, it could be any variable name.

And thank you for your feedback, walker!