Circuit for Clock Divide by 5 and 50 % duty cycle (urgent)

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spartanthewarrior

Joined: 13 Jun 2007
Posts: 97

23 Jul 2009 15:58 divide by 5 circuit

Hi All,

Please help me it's urgent.................

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AdvaRes

Joined: 14 Feb 2008
Posts: 1038
Helped: 46
Location: At home

23 Jul 2009 16:35 divide by 5

http://www.edaboard.com/viewtopic.php?p=805549#805549

arvkum02

Joined: 14 Mar 2008
Posts: 4

23 Oct 2009 7:36 Re: Circuit for Clock Divide by 5 and 50 % duty cycle (urgen

The basic way to design is :

First design a normal divide by N (here N=5) or mod N counter .
Analyses all the waveforms from the flops O/P.
Take a waveform that is high for (N-1)/2 (here 2) clock cycles (over a period of N cycles).

Delay this waveform or flop o/p by half of the clock period (give this signal as an input to a -ve edge triggred flop , the o/p will be delayed by half clock period).

Add the delayed and non delayed signal you will get desired o/p.

Feel free to ask further.

Arvind

koggestone

Joined: 16 Oct 2008
Posts: 31
Helped: 2

23 Oct 2009 14:34 Re: Circuit for Clock Divide by 5 and 50 % duty cycle (urgen

as suggested by arvkum02 in above reply , the steps are

1) generate straight forward div-by-5 with 40% duty cycle.
lets say its clkA.

2) feed this clkA to -ve edge triggerd flop . lets say the output is clkB.

3) required 50% duty cycle clk is OR of clkA and clkB.
clk50 = clkA | clkB;

Below is a pseudo code . u can use similar format for div-by-3/7/9/ etc ...

=========================

reg [2:0] count;
always @(posedge clk or negedge reset_n)
if (~reset_n)
count<=0;
else if (count == 3'd4)
count<=0;
else
count <=count+1;

assign clkA = count[1];

always@(negedge clk)
clkB <= clkA;

assign clk50 = clkA | clkB;

============================

In case , they ask u this question in interview ( Which 80% of time this will)
and u get hired , then Thank me (and arvkum2) in your Heart!!.

rakko

Joined: 01 Jun 2001
Posts: 244
Helped: 2
Location: mozambic

11 Nov 2009 4:42 Re: Circuit for Clock Divide by 5 and 50 % duty cycle (urgen

start two counters (LFSR is better) at the same time, one running from positive edge of the clock and the other from negative. When the positive edge counter is 2 and negative edge one is 3, toggle your output, reset both counters, and repeat. works for divide by any number.

2-bit counters.