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bobjee
Joined: 02 Jun 2009
Posts: 6
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 22 Jul 2009 0:00 asic projects |
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Hi All,
I need to design a project spec for a course. The course needs a design project which requires verilog. The verilog code is to be synthesized using cadence. Can some one suggest me good projects or some ideas on which I can design the spec on.
Thank you
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ljxpjpjljx
Joined: 05 May 2008
Posts: 534
Helped: 12
Location: Shang Hai
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22 Jul 2009 3:22 asic+projects |
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| how much size does your design need?
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bobjee
Joined: 02 Jun 2009
Posts: 6
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22 Jul 2009 3:25 asic projects |
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Hi,
The project must be a course project. It must take 8 to 10 weeks to complete the project.
It would be great if the project idea can be useful for real time applications.
Thank you
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pgbackup
Joined: 07 May 2009
Posts: 8
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22 Jul 2009 6:12 asic projects ideas |
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Check out opencores.org. Many of the cores there are synthesizable.
A good project might be a ALU supporting IEEE-754 adder/sub, mult, div
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22 Jul 2009 6:12 Ads |
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bobjee
Joined: 02 Jun 2009
Posts: 6
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22 Jul 2009 17:03 Re: Help with ASIC projects |
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Hi,
I have checked opencores.org. I have found some interesting projects over there. But I don't think they can be used as a course project. Can some one help me out with few more ideas.
Thank you
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pini_1
Joined: 18 Jun 2007
Posts: 288
Helped: 17
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22 Jul 2009 20:37 Re: Help with ASIC projects |
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USB full speed final project proposal
http://bknpk.no-ip.biz/usb_invitation_for_final_pj.html
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